EP2SGX30CF780C5N Altera, EP2SGX30CF780C5N Datasheet - Page 42
![IC STRATIX II GX 30K 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP2SGX30CF780C5N
Manufacturer Part Number
EP2SGX30CF780C5N
Description
IC STRATIX II GX 30K 780-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX30CF780C5N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
361
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
780-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
33880
# I/os (max)
361
Frequency (max)
609.76MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1750
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX30CF780C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Transceivers
Figure 2–27. Stratix II GX Block in Reverse Serial Pre-CDR Loopback Mode
Figure 2–28. Stratix II GX Block in PCI Express PIPE Reverse Parallel Loopback Mode
2–34
Stratix II GX Device Handbook, Volume 1
FPGA
Logic
Array
FPGA
Logic
Array
Transmitter Digital Logic
Receiver Digital Logic
Transmitter Digital Logic
Receiver Digital Logic
Incremental
Incremental
Generator
Incremental
Incremental
RX Phase
Generator
Compen-
RX Phase
Verify
Compen-
BIST
BIST
sation
FIFO
Verify
BIST
BIST
sation
FIFO
Compensation
Compensation
TX Phase
TX Phase
FIFO
FIFO
Ordering
Ordering
Serializer
Serializer
Byte
Byte
Byte
Byte
Figure 2–27
loopback mode.
PCI Express PIPE Reverse Parallel Loopback
This loopback mode, available only in PIPE mode, can be dynamically
enabled by the tx_detectrxloopback port of the PIPE interface.
Figure 2–28
20
20
serializer
serializer
Byte
De-
Byte
Encoder
De-
8B/10B
Encoder
8B/10B
PCI Express PIPE
show the Stratix II GX block in reverse serial pre-CDR
shows the datapath for this mode.
Reverse Parallel
Decoder
8B/10B
Decoder
Loopback
8B/10B
Generator
Generator
PRBS
BIST
PRBS
BIST
Match
FIFO
Rate
Match
Rate
FIFO
Deskew
Deskew
FIFO
FIFO
PRBS
Verify
BIST
PRBS
Verify
BIST
Aligner
Word
Aligner
Word
Analog Receiver and
Transmitter Logic
Analog Receiver and
Transmitter Logic
Serializer
serializer
Serializer
serializer
De-
De-
Altera Corporation
Reverse
Serial
Pre-CDR
Loopback
Recovery
Recovery
October 2007
Clock
Clock
Unit
Unit
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