EP2AGX65DF29C6N Altera, EP2AGX65DF29C6N Datasheet - Page 2
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EP2AGX65DF29C6N
Manufacturer Part Number
EP2AGX65DF29C6N
Description
IC ARRIA II GX FPGA 65K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX65DF29C6N.pdf
(306 pages)
Specifications of EP2AGX65DF29C6N
Number Of Logic Elements/cells
60214
Number Of Labs/clbs
2530
Total Ram Bits
5246
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
63250
# I/os (max)
364
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
63250
Ram Bits
5557452.8
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX65DF29C6N
Manufacturer:
ST
Quantity:
12 000
Page 2
Table 1. Family Issues for the Arria II GX Devices (Part 2 of 2)
Transmitter PLL Lock (pll_locked) Status Signal
Figure 1. Reference Clock Pre-Dividers in Transmitter PLLs
Errata Sheet for Arria II GX Devices
Error Detection CRC Feature
When enabled, the Error Detection CRC feature may cause the
MLAB RAM blocks to operate incorrectly.
M9K RAM Block Lock-Up
The M9K RAM blocks may lock up due to a glitchy non-PLL
clock.
Automatic Clock Switchover
The automatic clock switchover feature may not operate correctly.
Remote System Upgrade
The remote system upgrade feature fails when loading an invalid
configuration image.
Input Reference
Clock
f
The transmitter phase-locked loop (PLL) lock status signal (pll_locked) does not
de-assert when the pll_powerdown signal is asserted in configurations that use the
reference clock pre-divider of 2, 4, or 8.
inside transmitter PLLs. This issue impacts the pll_locked status signal in the clock
multiplier unit (CMU) PLL.
Designs that implement the recommended transceiver reset sequence described in the
Reset Control and Power Down in Arria II Devices
Device Handbook could potentially see a link failure after coming out of reset.
Reference Clock
/1, /2, /4, /8
Pre-Divider
Issue
Detect
Lock
PFD
Charge Pump
Loop Filter
CMU PLL
+
/M
Figure 1
Affected Devices
EP2AGX125 ES
EP2AGX125 ES
EP2AGX125 ES
EP2AGX125 ES
VCO
chapter in volume 2 of the Arria II
shows the reference clock pre-divider
Transmitter PLL Lock (pll_locked) Status Signal
/L
February 2011 Altera Corporation
EP2AGX125 production
EP2AGX125 production
High-Speed
CMU0
Clock
Planned Fix
Software fix
devices
devices
None
pll_locked