EP2AGX45DF29I5N Altera, EP2AGX45DF29I5N Datasheet - Page 21
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EP2AGX45DF29I5N
Manufacturer Part Number
EP2AGX45DF29I5N
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX45DF29I5N.pdf
(306 pages)
Specifications of EP2AGX45DF29I5N
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
45125
# I/os (max)
364
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
45125
Ram Bits
3565158.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
853
Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
Table 1–30. Differential HSTL I/O Standards for Arria II GX Devices
Table 1–31. Differential HSTL I/O Standards for Arria II GZ Devices
Table 1–32. Differential I/O Standard Specifications for Arria II GX Devices
December 2010 Altera Corporation
HSTL-18 Class I
HSTL-15 Class I, II
HSTL-12 Class I, II
HSTL-18 Class I
HSTL-15 Class I, II
HSTL-12 Class I, II
2.5 V
LVDS
RSDS
Mini-
LVDS
LVPECL
Notes to
(1) The 1.5 V PCML transceiver I/O standard specifications are described in
(2) V
(3) R
(4) The RSDS and mini-LVDS I/O standards are only supported for differential outputs.
(5) The LVPECL input standard is supported at the dedicated clock input pins (GCLK) only.
Standard
(4)
(5)
I/O
I/O Standard
I/O Standard
IN
L
(4)
range: 90 <= RL <= 110 .
range: 0 <= V
Table
2.375
2.375
2.375
2.375
Min
1–32:
V
IN
CCIO
<= 1.85 V.
Typ
2.5 2.625
2.5 2.625
2.5 2.625
2.5 2.625
Table 1–30
Table 1–31
Table 1–32
(V)
1.425
1.425
1.71
1.14
1.71
1.14
Min
Min
Max
V
V
CCIO
CCIO
Typ
1.8
1.5
1.2
Typ
1.8
1.5
1.2
(V)
Min
100
300
lists the HSTL I/O standards for Arria II GX devices.
lists the HSTL I/O standards for Arria II GZ devices.
lists the differential I/O standard specifications for Arria II GX devices.
(V)
—
—
1.575
Max
1.89
1.26
1.575
1.89
1.26
Max
V
TH
1.25 V
Cond.
V
CM
—
—
—
(mV)
0.16
Min
0.2
0.2
=
V
0.16
Min
0.2
0.2
DIF(DC)
V
DIF(DC)
Max
—
—
—
—
—
Max
—
—
—
(V)
V
+ 0.3
Max
(V)
—
—
CCIO
0.05
1.05
Min
0.6
1.0
—
—
0.85
0.71
Min
—
0.78
0.68
Min
—
“Transceiver Performance Specifications” on page
V
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
700 Mbps
700 Mbps
700 Mbps
700 Mbps
ICM
V
D
D
Cond.
D
D
X(AC)
0.5 ×
V
max
max
Typ
max
max
—
V
—
—
—
CCIO
(V)
X(AC)
0.5 ×
V
<=
<=
Typ
—
—
>
>
(V)
CCIO
(2)
(V)
Max
0.95
0.79
—
(Note 1)
Max
1.80
1.55
1.8
1.6
—
—
1.12
Max
0.9
—
V
0.88
0.71
0.48
Min
0.247
CCIO
×
0.25
Min
0.1
—
0.4 ×
V
0.78
0.68
Min
CCIO
V
V
CM(DC)
OD
0.5 ×
V
Typ
Typ
0.2
—
—
CCIO
(V)
—
—
—
V
CM(DC)
0.5 ×
V
(V)
Typ
(3)
—
—
CCIO
Max
0.52 ×
0.6
0.6
0.6
—
V
Max
0.95
0.79
(V)
CCIO
0.6 ×
V
1.12
Max
1–21.
0.9
1.125
CCIO
Min
0.5
—
Min
1
0.4
0.4
0.3
V
DIF(AC)
V
Min
0.4
0.4
0.3
V
1.25
OS
Typ
1.2
1.2
Max
—
DIF(AC)
(V)
—
—
—
1–19
(V)
V
0.48
Max
(V)
1.375
—
—
CCIO
Max
+
1.4
1.4
—