EP2S30F484I4N Altera, EP2S30F484I4N Datasheet - Page 61
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EP2S30F484I4N
Manufacturer Part Number
EP2S30F484I4N
Description
IC STRATIX II FPGA 30K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F484I4N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
342
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
33880
# I/os (max)
342
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
33880
Ram Bits
1369728
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1894
EP2S30F484I4N
EP2S30F484I4N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F484I4N
Manufacturer:
FREESCALE
Quantity:
101
Company:
Part Number:
EP2S30F484I4N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S30F484I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 2–36. EP2S60, EP2S90, EP2S130 & EP2S180 Device I/O Clock Groups
Altera Corporation
May 2007
IO_CLKM[7:0]
IO_CLKO[7:0]
IO_CLKN[7:0]
IO_CLKP[7:0]
8
8
8
8
IO_CLKA[7:0]
8
You can use the Quartus II software to control whether a clock input pin
drives either a global, regional, or dual-regional clock network. The
Quartus II software automatically selects the clocking resources if not
specified.
Clock Control Block
Each global clock, regional clock, and PLL external clock output has its
own clock control block. The control block has two functions:
■
■
IO_CLKL[7:0]
24 Clocks in the
24 Clocks in the
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable/disable)
8
Quadrant
Quadrant
IO_CLKB[7:0]
8
IO_CLKK[7:0]
8
IO_CLKC[7:0]
8
IO_CLKJ[7:0]
24 Clocks in the
24 Clocks in the
8
Quadrant
Quadrant
IO_CLKD[7:0]
Stratix II Device Handbook, Volume 1
8
IO_CLKI[7:0]
8
8
8
8
8
Stratix II Architecture
IO_CLKE[7:0]
IO_CLKF[7:0]
IO_CLKG[7:0]
IO_CLKH[7:0]
I/O Clock Regions
2–53