EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 71
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Figure 2–32. Multiplier Sub-Block within Stratix DSP Block
Note to
(1)
Altera Corporation
July 2005
These signals can be unregistered or registered once to match data path pipelines if required.
Figure
Data B
Data A
2–32:
shiftout B
shiftin B
shiftout A
The DSP block consists of the following elements:
■
■
Multiplier Block
The DSP block multiplier block consists of the input registers, a
multiplier, and pipeline register for pipelining multiply-accumulate and
multiply-add/subtract functions as shown in
ENA
ENA
D
D
Multiplier block
Adder/output block
CLRN
CLRN
clock[3..0]
sign_a (1)
sign_b (1)
shiftin A
aclr[3..0]
ena[3..0]
Q
Q
ENA
D
CLRN
Q
Stratix Device Handbook, Volume 1
Figure
Optional
Multiply-Accumulate
and Multiply-Add
Pipeline
Result
to Adder
blocks
2–32.
Stratix Architecture
2–57
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