EP2AGX95EF29C4N Altera, EP2AGX95EF29C4N Datasheet - Page 3

• Manufacturer Part Number: EP2AGX95EF29C4N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29C4N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Transmitter PLL Lock (pll_locked) Status Signal
Figure 2. Determining Reference Clock Pre-Divider Value in the Compilation Report
Figure 3. Instantiating and Connecting the pll_locked_soft_logic Module
February 2011 Altera Corporation
xcvr_async_reset
top_cal_blk_clk
top_pll_inclk
system_clk
Workaround
f
inst3
xcvr_reset_logic
xcvr_async_reset
clk
pll_locked
You can determine if the Transmitter PLL in your design uses a reference clock
pre-divider of 2, 4, or 8 by referring to the Quartus
Figure 2
the “Resources Section” under “Fitter” in the Compilation Report. If the value in the
“Divide By” column reads 2, 4, or 8, your design is impacted by the pll_locked status
signal issue.
If the pll_locked issue impacts your design, instantiate and connect the
pll_locked_soft_logic module, as shown in
pll_locked_to_corelogic output from this module must be used in the transceiver
reset logic and any user logic that relies on the transmitter PLL lock status signal.
Click
pll_locked_soft_logic
shows an example of the “GXB Transmitter PLL” report, which you find in
pll_powerdown
tx_digitalreset
tx_datain[39..0]
to obtain the module.
pll_locked_soft_logic
serdes_io
inst2
inst
cal_blk_clk
pll_inclk
pll_powerdown[0..0]
tx_datain[39..0]
tx_digitalreset[0..0]
clk
reset
pll_locked_from_altgx
Figure
®
II software Compilation Report.
pll_locked_to_corelogic
3. The
tx_dataout[0..0]
pll_locked[0..0]
tx_clkout[0..0]
Errata Sheet for Arria II GX Devices
top_tx_dataout
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