EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 2
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Page 2
Table 1. Family Issues for the Arria II GX Devices (Part 2 of 2)
Transmitter PLL Lock (pll_locked) Status Signal
Figure 1. Reference Clock Pre-Dividers in Transmitter PLLs
Errata Sheet for Arria II GX Devices
Error Detection CRC Feature
When enabled, the Error Detection CRC feature may cause the
MLAB RAM blocks to operate incorrectly.
M9K RAM Block Lock-Up
The M9K RAM blocks may lock up due to a glitchy non-PLL
clock.
Automatic Clock Switchover
The automatic clock switchover feature may not operate correctly.
Remote System Upgrade
The remote system upgrade feature fails when loading an invalid
configuration image.
Input Reference
Clock
f
The transmitter phase-locked loop (PLL) lock status signal (pll_locked) does not
de-assert when the pll_powerdown signal is asserted in configurations that use the
reference clock pre-divider of 2, 4, or 8.
inside transmitter PLLs. This issue impacts the pll_locked status signal in the clock
multiplier unit (CMU) PLL.
Designs that implement the recommended transceiver reset sequence described in the
Reset Control and Power Down in Arria II Devices
Device Handbook could potentially see a link failure after coming out of reset.
Reference Clock
/1, /2, /4, /8
Pre-Divider
Issue
Detect
Lock
PFD
Charge Pump
Loop Filter
CMU PLL
+
/M
Figure 1
Affected Devices
EP2AGX125 ES
EP2AGX125 ES
EP2AGX125 ES
EP2AGX125 ES
VCO
chapter in volume 2 of the Arria II
shows the reference clock pre-divider
Transmitter PLL Lock (pll_locked) Status Signal
/L
February 2011 Altera Corporation
EP2AGX125 production
EP2AGX125 production
High-Speed
CMU0
Clock
Planned Fix
Software fix
devices
devices
None
pll_locked