EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 64
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
1–62
Table 1–46. DSP Block Performance Specifications for Arria II GX Devices
Table 1–47. DSP Block Performance Specifications for Arria II GZ Devices
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
9 × 9-bit multiplier
12 × 12-bit multiplier
18 × 18-bit multiplier
36 × 36-bit multiplier
18 × 36-bit high-precision multiplier
adder mode
18 × 18-bit multiply accumulator
18 × 18-bit multiply adder
18 × 18-bit multiply adder-signed full
precision
18 × 18-bit multiply adder with
loopback
36-bit shift (32-bit data)
Double mode
Notes to
(1) Maximum is for a fully-pipelined block with Round and Saturation disabled.
(2) Maximum is for loopback input registers disabled, Round and Saturation disabled, pipeline and output registers enabled.
9 × 9-bit multiplier
12 × 12-bit multiplier
18 × 18-bit multiplier
36 × 36-bit multiplier
18 × 18-bit multiply accumulator
18 × 18-bit multiply adder
18 × 18-bit multiply adder-signed full
precision
18 × 18-bit multiply adder with
loopback
36-bit shift (32-bit data)
Table
(2)
(2)
1–46:
Mode
Mode
DSP Block Specifications
Table 1–46
Table 1–47
lists the DSP block performance specifications for Arria II GX devices.
lists the DSP block performance specifications for Arria II GZ devices.
Multipliers
Resources
Number of
Multipliers
Resources
Number of
Used
Used
1
1
1
1
1
4
4
2
2
1
1
4
4
1
1
1
1
2
2
1
380
380
380
350
350
380
380
380
275
350
350
C4
500
550
440
440
470
440
460
450
350
–3
310
310
310
270
270
310
310
310
220
270
270
I3
(Note 1)
(Note 1)
Performance
Performance
Chapter 1: Device Datasheet for Arria II Devices
C5,I5
300
300
300
270
270
300
300
300
220
270
270
December 2010 Altera Corporation
400
440
480
380
380
410
390
310
380
–4
Switching Characteristics
250
250
250
220
220
250
250
250
180
220
220
C6
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
MHz