EP20K600EFC672-2N Altera, EP20K600EFC672-2N Datasheet - Page 74

• Manufacturer Part Number: EP20K600EFC672-2N
• Description: IC APEX 20KE FPGA 600K 672-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K600EFC672-2N

• Number Of Logic Elements/cells: 24320
• Number Of Labs/clbs: 2432
• Total Ram Bits: 311296
• Number Of I /o: 508
• Number Of Gates: 1537000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APEX 20K Programmable Logic Device Family Data Sheet
Note to
(1)
74
These timing parameters are sample-tested only.
Tables 32
and 33:
Tables 34
timing microparameters for the f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SU
H
CO
LUT
ESBARC
ESBSRC
ESBAWC
ESBSWC
ESBWASU
ESBWAH
ESBWDSU
ESBWDH
ESBRASU
ESBRAH
ESBWESU
ESBWEH
ESBDATASU
ESBDATAH
ESBWADDRSU
ESBRADDRSU
ESBDATACO1
ESBDATACO2
ESBDD
PD
PTERMSU
PTERMCO
Table 34. APEX 20KE LE Timing Microparameters
Table 35. APEX 20KE ESB Timing Microparameters
Symbol
Symbol
through
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LUT delay for data-in to data-out
ESB Asynchronous read cycle time
ESB Synchronous read cycle time
ESB Asynchronous write cycle time
ESB Synchronous write cycle time
ESB write address setup time with respect to WE
ESB write address hold time with respect to WE
ESB data setup time with respect to WE
ESB data hold time with respect to WE
ESB read address setup time with respect to RE
ESB read address hold time with respect to RE
ESB WE setup time before clock when using input register
ESB WE hold time after clock when using input register
ESB data setup time before clock when using input register
ESB data hold time after clock when using input register
ESB write address setup time before clock when using input
registers
ESB read address setup time before clock when using input
registers
ESB clock-to-output delay when using output registers
ESB clock-to-output delay without output registers
ESB data-in to data-out delay for RAM mode
ESB Macrocell input to non-registered output
ESB Macrocell register setup time before clock
ESB Macrocell register clock-to-output delay
37
show APEX 20KE LE, ESB, routing, and functional
MAX
timing model.
Parameter
Parameter
Altera Corporation