EP2S60F672I4 Altera, EP2S60F672I4 Datasheet - Page 169

• Manufacturer Part Number: EP2S60F672I4
• Description: IC STRATIX II FPGA 60K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S60F672I4

• Number Of Logic Elements/cells: 60440
• Number Of Labs/clbs: 3022
• Total Ram Bits: 2544192
• Number Of I /o: 492
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 60440
• # I/os (max): 492
• Frequency (max): 711.24MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 60440
• Ram Bits: 2544192
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• For Use With: 544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1915; EP2S60F672I4

Altera Corporation
April 2011
Notes for
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Larger
designs
Table 5–36. Stratix II Performance Notes (Part 6 of 6)
These design performance numbers were obtained using the Quartus II software version 5.0 SP1.
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
This application uses registered inputs and outputs.
This application uses registered multiplier input and output stages within the DSP block.
This application uses registered multiplier input, pipeline, and output stages within the DSP block.
This application uses registered multiplier input with output of the multiplier stage feeding the accumulator or
subtractor within the DSP block.
This application uses the same clock source that is globally routed and connected to ports A and B.
This application uses locally routed clocks or differently sourced clocks for ports A and B.
Table
Applications
8-bit, 1024-point,
quadrant output, four
parallel FFT engines,
buffered burst, three
multipliers five adders
FFT function
8-bit, 1024-point,
quadrant output, four
parallel FFT engines,
buffered burst, four
multipliers and two
adders FFT function
5–36:
ALUTs
7385
6601
Resources Used
TriMatrix
Memory
Blocks
60
60
Blocks
DSP
36
48
Note (1)
359.58
371.88
Speed
Grade
(2)
-3
Stratix II Device Handbook, Volume 1
352.98
355.74
Speed
Grade
DC & Switching Characteristics
(3)
-3
Performance
312.01
327.86
Speed
Grade
-4
278.00
277.62
Speed
Grade
-5
MHz
MHz
Unit
5–33