EP1S40B956C6 Altera, EP1S40B956C6 Datasheet - Page 97
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EP1S40B956C6
Manufacturer Part Number
EP1S40B956C6
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S40B956C6
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1423
EP1S40SB956C6
EP1S40SB956C6
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S40B956C6
Manufacturer:
ALTERA
Quantity:
260
Company:
Part Number:
EP1S40B956C6
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S40B956C6
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1S40B956C6N
Manufacturer:
ALTERA
Quantity:
229
Part Number:
EP1S40B956C6N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
July 2005
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Clock multiplication and division
Phase shift
Delay shift
Clock switchover
PLL reconfiguration
Programmable bandwidth
Spread spectrum clocking
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Number of feedback clock inputs
Table 2–19. Stratix PLL Features
For enhanced PLLs, m, n, range from 1 to 512 and post-scale counters g, l, e range from 1 to 1024 with 50% duty
cycle. With a non-50% duty cycle the post-scale counters g, l, e range from 1 to 512.
For fast PLLs, m and post-scale counters range from 1 to 32.
The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.
For degree increments, Stratix devices can shift all output frequencies in increments of at least 45
increments are possible depending on the frequency and divide parameters.
PLLs 7, 8, 9, and 10 have two output ports per PLL. PLLs 1, 2, 3, and 4 have three output ports per PLL.
Every Stratix device has two enhanced PLLs (PLLs 5 and 6) with either eight single-ended outputs or four
differential outputs each. Two additional enhanced PLLs (PLLs 11 and 12) in EP1S80, EP1S60, and EP1S40 devices
each have one single-ended output. Devices in the 780 pin FineLine BGA packages do not support PLLs 11 and 12.
Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
Every Stratix device has two enhanced PLLs with one single-ended or differential external feedback input per PLL.
Table
Feature
2–19:
Table 2–19
devices.
Down to 156.25-ps increments (3),
Four differential/eight singled-ended
m/(n × post-scale counter)
250-ps increments for ±3 ns
shows the enhanced PLL and fast PLL features in Stratix
or one single-ended
Enhanced PLL
2
v
v
v
v
v
6
(8)
(6)
(1)
(4)
Stratix Device Handbook, Volume 1
Down to 125-ps increments (3),
m/(post-scale counter)
Fast PLL
3
Stratix Architecture
v
(7)
(5)
°
. Smaller degree
(2)
2–83
(4)