EP1S60F1020C7N Altera, EP1S60F1020C7N Datasheet - Page 71
EP1S60F1020C7N
Manufacturer Part Number
EP1S60F1020C7N
Description
IC STRATIX FPGA 60K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S60F1020C7N
Number Of Logic Elements/cells
57120
Number Of Labs/clbs
5712
Total Ram Bits
5215104
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
EP1S60F1020C7N
Manufacturer:
ALTERA
Quantity:
591
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Figure 2–32. Multiplier Sub-Block within Stratix DSP Block
Note to
(1)
Altera Corporation
July 2005
These signals can be unregistered or registered once to match data path pipelines if required.
Figure
Data B
Data A
2–32:
shiftout B
shiftin B
shiftout A
The DSP block consists of the following elements:
■
■
Multiplier Block
The DSP block multiplier block consists of the input registers, a
multiplier, and pipeline register for pipelining multiply-accumulate and
multiply-add/subtract functions as shown in
ENA
ENA
D
D
Multiplier block
Adder/output block
CLRN
CLRN
clock[3..0]
sign_a (1)
sign_b (1)
shiftin A
aclr[3..0]
ena[3..0]
Q
Q
ENA
D
CLRN
Q
Stratix Device Handbook, Volume 1
Figure
Optional
Multiply-Accumulate
and Multiply-Add
Pipeline
Result
to Adder
blocks
2–32.
Stratix Architecture
2–57
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