EP2SGX90EF1152C5N Altera, EP2SGX90EF1152C5N Datasheet - Page 246

• Manufacturer Part Number: EP2SGX90EF1152C5N
• Description: IC STRATIX II GX 90K 1152-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX90EF1152C5N

• Number Of Logic Elements/cells: 90960
• Number Of Labs/clbs: 4548
• Total Ram Bits: 4520448
• Number Of I /o: 558
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 1152-FBGA
• For Use With: 544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1768; EP2SGX90EF35C5NES

Timing Model
4–76
Stratix II GX Device Handbook, Volume 1
t
t
t
t
t
t
t
t
C I N
C O U T
P L L C I N
P L L C O U T
C I N
C O U T
P L L C I N
P L L C O U T
Table 4–63. EP2SGX30 Column Pins Global Clock Timing Parameters
Table 4–64. EP2SGX30 Row Pins Global Clock Timing Parameters
Parameter
Parameter
Industrial
Industrial
-0.055
-0.151
-0.146
1.615
1.450
1.365
1.370
0.11
Fast Corner
Fast Corner
Stratix II GX Clock Timing Parameters
See
EP2SGX30 Clock Timing Parameters
Tables 4–63
for EP2SGX30 devices.
t
t
t
t
CIN
COUT
PLLCIN
PLLCOUT
Table 4–62. Stratix II GX Clock Timing Parameters
Commercial
Commercial
Tables 4–62
Symbol
-0.036
-0.136
-0.131
1.633
1.468
0.129
1.382
1.387
through
through
Delay from clock pad to I/O input register
Delay from clock pad to I/O output register
Delay from PLL
Delay from PLL
-3 Speed
-3 Speed
Grade
Grade
2.669
2.427
0.428
0.186
2.280
2.276
0.043
0.039
4–66
4–78
show the maximum clock timing parameters
for Stratix II GX clock timing parameters.
inclk
inclk
-4 Speed
-4 Speed
Grade
Grade
2.968
2.698
0.466
0.196
2.535
2.531
0.037
0.033
pad to I/O input register
pad to I/O output register
Parameter
-5 Speed
-5 Speed
Grade
Grade
3.552
3.228
0.547
0.223
3.033
3.028
0.032
0.027
Altera Corporation
June 2009
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns