EP1SGX40GF1020C5 Altera, EP1SGX40GF1020C5 Datasheet - Page 89

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EP1SGX40GF1020C5

Manufacturer Part Number
EP1SGX40GF1020C5
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet

Specifications of EP1SGX40GF1020C5

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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Altera Corporation
February 2005
single block of RAM ideal for data packet storage. The different-sized
blocks allow Stratix GX devices to efficiently support variable-sized
memory in designs.
The Quartus II software automatically partitions the user-defined
memory into the embedded memory blocks using the most efficient size
combinations. You can also manually assign the memory to a specific
block size or a mixture of block sizes.
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful
for implementing small FIFO buffers, DSP, and clock domain transfer
applications. Each block contains 576 RAM bits (including parity bits).
M512 RAM blocks can be configured in the following modes:
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
The memory address depths and output widths can be configured as
512 × 1, 256 × 2, 128 × 4, 64 × 8 (64 × 9 bits with parity), and 32 × 16
(32 × 18 bits with parity). Mixed-width configurations are also possible,
allowing different read and write widths.
possible M512 RAM block configurations.
Read Port
Table 4–3. M512 RAM Block Configurations (Simple Dual-Port RAM)
512
256
128
32
32
64
64
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
×
×
×
×
×
×
×
16
18
8
9
1
2
4
512 × 1
v
v
v
v
v
256 × 2
v
v
v
v
v
128 × 4
v
v
v
v
Stratix GX Device Handbook, Volume 1
Write Port
64 × 8
v
v
v
Table 4–3
32 × 16
v
v
v
v
Stratix GX Architecture
summarizes the
64 × 9
v
32 × 18
v
4–23

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