EP2S90F1020C3 Altera, EP2S90F1020C3 Datasheet - Page 83
EP2S90F1020C3
Manufacturer Part Number
EP2S90F1020C3
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S90F1020C3
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1917
EP2S90F1020C3
EP2S90F1020C3
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Figure 2–50. Control Signal Selection per IOE
Notes to
(1)
Altera Corporation
May 2007
Dedicated I/O
Clock [7..0]
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their
control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive
the I/O local interconnect, which then drives the control selection multiplexers.
Figure
2–50:
io_oe
io_sclr
io_aclr
io_ce_out
io_ce_in
io_clk
In normal bidirectional operation, the input register can be used for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register can be used for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
dedicated I/O clocks, and the column and row interconnects.
clk_in
clk_out
ce_in
Stratix II Device Handbook, Volume 1
ce_out
aclr/apreset
Stratix II Architecture
sclr/spreset
oe
2–75
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