EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 15
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
Bussmann
Quantity:
40 000
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
ALTERA21
Quantity:
53
Production Devices for Stratix IV GX Devices
Figure 9. Setting Voltage Levels
March 2011 Altera Corporation
■
Category 3: The configured ×N line data rate is greater than the maximum data
rate supported by the 1.2-V power supply level specified in
The Quartus II Compiler flags the following compilation error:
"Error: Transceiver channels clocked by clock divider atom
"top_alt4gxb:top_alt4gxb_component|central_clk_div0" are configured at a data
rate that is higher than that supported in Stratix IV GX/GT devices. The data rate
limitation is due to a ×N clock line issue. For more details on the impact of ×N
clock line issue, refer to the Stratix IV GX or Stratix IV GT Errata sheet section "×8
and ×N Clock Line Timing Issue for Transceivers."
Action: In the Quartus II software, on the Assignments menu, click Settings. Click
the “+” icon to expand Operating Settings and Conditions and select Voltage. Set
the VCCT_L/R, VCCL_GXBL/R, and VCCR_L/R voltage settings from 1.1V to
1.2V, as shown in
The Quartus II Compiler flags the following compilation error:
"Error: Transceiver channels clocked by clock divider atom
"top_alt4gxb:top_alt4gxb_component|central_clk_div0" are configured at a data
rate that is higher than that supported in Stratix IV GX/GT devices. The data rate
limitation is due to a ×N clock line issue. For more information about the impact of
×N clock line issue, refer to the Stratix IV GX or Stratix IV GT Errata sheet section
"×8 and ×N Clock Line Timing Issue for Transceivers."
Figure
9. Then recompile the project.
Errata Sheet for Stratix IV GX Devices
Table
2.
Page 15