EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 65
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
Bussmann
Quantity:
40 000
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
ALTERA21
Quantity:
53
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Glossary
Glossary
Table 1–53. Glossary Table (Part 1 of 4)
April 2011 Altera Corporation
A, B, C
G, H, I
Letter
D
E
F
Differential I/O
Standards
f
f
f
HSCLK
HSDR
HSDRDPA
Subject
—
—
—
Table 1–53
Receiver Input Waveforms
Transmitter Output Waveforms
Left/right PLL input clock frequency.
High-speed I/O block: Maximum/minimum LVDS data transfer rate
(f
High-speed I/O block: Maximum/minimum LVDS data transfer rate
(f
Single-Ended Waveform
Differential Waveform
Single-Ended Waveform
Differential Waveform
HSDR
HSDRDPA
lists the glossary for this chapter.
= 1/TUI), non-DPA.
= 1/TUI), DPA.
V
V
CM
CM
V
V
ID
OD
V
V
ID
OD
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Definitions
—
—
—
V
V
ID
OD
p − n = 0 V
p − n = 0 V
Positive Channel (p) = V
Negative Channel (n) = V
Ground
Positive Channel (p) = V
Negative Channel (n) = V
Ground
IH
OH
IL
OL
1–63