EP4SGX290KF40C3N Altera, EP4SGX290KF40C3N Datasheet - Page 312
EP4SGX290KF40C3N
Manufacturer Part Number
EP4SGX290KF40C3N
Description
IC STRATIX IV GX 290K 1517FBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX290KF40C3N
Number Of Logic Elements/cells
291200
Number Of Labs/clbs
11648
Total Ram Bits
17248
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1517-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2624
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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8–34
Figure 8–27. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA Mode
Stratix IV Device Handbook Volume 1
Timing Diagram
External
Input Clock
Internal
Clock
Receiver
Input Data
Timing Budget
External
Clock
Internal
Clock
Synchronization
Transmitter
Output Data
Receiver
Input Data
TCCS
Figure 8–27
You must calculate the RSKM value to decide whether or not data can be sampled
properly by the LVDS receiver with the given data rate and device. A positive RSKM
value indicates that the LVDS receiver can sample the data properly, whereas a
negative RSKM indicates that it cannot.
shows the relationship between the RSKM, TCCS, and the receiver’s SW.
TCCS
RSKM
RSKM
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Time Unit Interval (TUI)
Clock Placement
Falling Edge
SW
Internal
TUI
SW
Clock
RSKM
RSKM
TCCS
Source-Synchronous Timing Budget
February 2011 Altera Corporation
TCCS
2
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