EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 84

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EP4SE530H35C2N

Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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4–4
Stratix IV Simplified DSP Operation
Stratix IV Device Handbook Volume 1
1
In Stratix IV devices, the fundamental building block is a pair of 18 × 18-bit
multipliers followed by a first-stage 37-bit addition/subtraction unit, as shown in
Equation 4–1
All signed numbers, input, and output data are represented in 2’s-complement format
only.
Equation 4–1. Multiplier Equation
Figure 4–2. Basic Two-Multiplier Adder Building Block
The structure shown in
such as complex multipliers and 36 × 36 multipliers, as described in later sections.
Each Stratix IV DSP block contains four two-multiplier adder units (2 two-multiplier
adder units per half block). Therefore, there are eight 18 × 18 multiplier functionalities
per DSP block.
A0[17..0]
B0[17..0]
A1[17..0]
B1[17..0]
and
Figure
P[36..0] = A
Figure 4–2
D
D
4–2.
Q
Q
0
[17..0] × B
is useful for building more complex structures,
0
[17..0] ± A
1
[17..0] × B
Chapter 4: DSP Blocks in Stratix IV Devices
+/-
1
[17..0]
Stratix IV Simplified DSP Operation
February 2011 Altera Corporation
P[36..0]

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