EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 67

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–45. DLL Frequency Range Specifications for Stratix IV Devices—Preliminary (Part 2 of 2)
April 2011 Altera Corporation
Note to
(1) Low indicates a 6-bit DQS delay setting; high indicates a 5-bit DQS delay setting.
Frequency
Mode
7
Table
1–45:
1
1
Speed Grade
470-700
–2/–2×
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column.
Table 1–46
Table 1–46. DQS Phase Offset Delay Per Setting for Stratix IV Devices
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column.
Table 1–47
Table 1–47. DQS Phase Shift Error Specification for DLL-Delayed Clock (t
Devices
Notes to
(1) The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes
(2) The typical value equals the average of the minimum and maximum values.
(3) The delay settings are linear, with a cumulative delay variation of 40 ps for all speed grades. For example, when
Note to
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
Number of DQS Delay
Frequency Range (MHz)
4 to 6.
using a –2 speed grade and applying a 10 phase offset settings to a 90° phase shift at 400 MHz, the expected
average cumulative delay is [625 ps + (10 × 10.5 ps) ± 20 ps] = 730 ps ± 20 ps.
buffers in a –2/–2x speed grade is ± 78 ps or ± 39 ps.
Table
Table
(Note 1)
Speed Grade
Buffer
Speed Grade
lists the DQS phase offset delay per stage for Stratix IV devices.
lists the DQS phase shift error for Stratix IV devices.
1–47:
–2/–2×
1
2
3
4
470-630
1–46:
–3
–4
–3
Speed Grade
470-590
–4
Speed Grade
–2/–2X
104
26
52
78
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Available Phase Shift
60°, 120°, 180°, 240°
Min
7
7
7
Speed Grade
112
–3
28
56
84
Max
13
15
16
DQS Delay Buffer
Speed Grade
Mode
(Note
DQS_PSERR
High
120
–4
30
60
90
1),
(1)
(2)
) for Stratix IV
,
Unit
(3)
ps
ps
ps
Number of
Chains
Unit
Delay
ps
ps
ps
ps
6
1–59