XC2S50E-6PQ208C Xilinx Inc, XC2S50E-6PQ208C Datasheet - Page 55

• Manufacturer Part Number: XC2S50E-6PQ208C
• Description: IC FPGA 1.8V 384 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-IIEr

Specifications of XC2S50E-6PQ208C

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 384
• Total Ram Bits: 32768
• Number Of I /o: 146
• Number Of Gates: 50000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Case: QFP208
• Dc: 03+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1205

Spartan-IIE Package Pinouts
The Spartan
lar, low-cost packages, including plastic quad flat packs and
fine-pitch ball grid arrays. Family members have footprint
compatibility across devices provided in the same package,
with minor exceptions due to the smaller number of I/O in
smaller devices or due to LVDS/LVPECL pin pairing. The
Table 12: Spartan-IIE Family Package Options
Package Overview
Table 12
package styles for the Spartan-IIE family.
Each package style is available in an environmentally
friendly lead-free (Pb-free) option. The Pb-free packages
include an extra ‘G’ in the package style name. For
example, the standard “TQ144” package becomes
“TQG144” when ordered as the Pb-free option. Leaded
(non-Pb-free) packages may be available for selected
devices, with the same pin-out and without the "G" in the
ordering code; contact Xilinx
The mechanical dimensions of the standard and Pb-free
packages are similar, as shown in the mechanical drawings
provided in
For additional package information, see UG112: Device
Package User Guide.
DS077-4 (2.3) June 18, 2008
Product Specification
Notes:
1.
TQ144 / TQG144
PQ208 / PQG208
FT256 / FTG256
FG456 / FGG456
FG676 / FGG676
Package mass is ±10%.
Package
shows the five low-cost, space-saving production
Table
R
®
-IIE family of FPGAs is available in five popu-
13.
Leads
144
208
256
456
676
Thin Quad Flat Pack (TQFP)
Plastic Quad Flat Pack (PQFP)
Fine-pitch Thin Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
Fine-pitch Ball Grid Array (FBGA)
®
sales for more information.
Type
www.xilinx.com
Spartan-IIE family is not footprint compatible with any other
FPGA family. The following package-specific pinout tables
indicate function, pin, and bank information for all devices
available in that package. The pinouts follow the pad loca-
tions around the die, starting from pin 1 on the QFP pack-
ages.
Mechanical Drawings
Detailed mechanical drawings for each package type are
available from the Xilinx web site at the specified location in
Table
Material Declaration Data Sheets (MDDS) are also
available on the
Table 13: Xilinx Package Documentation
Maximum
TQ144
TQG144
PQ208
PQG208
FT256
FTG256
FG456
FGG456
FG676
FGG676
102
146
182
329
514
I/O
Package
13.
Lead Pitch
(mm)
0.5
0.5
1.0
1.0
1.0
Xilinx web site
Spartan-IIE FPGA Family: Pinout Tables
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Package Drawing
Drawing
Area (mm)
30.6 x 30.6
Footprint
22 x 22
17 x 17
23 x 23
27 x 27
for each package.
PK169_TQ144
PK126_TQG144
PK166_PQ208
PK123_PQG208
PK158_FT256
PK115_FTG256
PK154_FG456
PK109_FGG456
PK155_FG676
PK111_FGG676
Height
(mm)
1.60
3.70
1.55
2.60
2.60
MDDS
Mass
1.4
5.3
1.0
2.2
3.1
(g)
(1)
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