XC3S500E-4VQG100I Xilinx Inc, XC3S500E-4VQG100I Datasheet - Page 112
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XC3S500E-4VQG100I
Manufacturer Part Number
XC3S500E-4VQG100I
Description
IC FPGA SPARTAN-3E 500K 100-VQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4VQG100I
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
66
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
100-TQFP
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4VQG100I
Manufacturer:
XILINX
Quantity:
2 360
Company:
Part Number:
XC3S500E-4VQG100I
Manufacturer:
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Quantity:
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Functional Description
Voltage Regulators
Various power supply manufacturers offer complete power
solutions for Xilinx FPGAs including some with integrated
three-rail regulators specifically designed for Spartan-3 and
Spartan-3E FPGAs. The
vides links to vendor solution guides and Xilinx power esti-
mation and analysis tools.
Power Distribution System (PDS) Design and
Decoupling/Bypass Capacitors
Good power distribution system (PDS) design is important
for all FPGA designs, but especially so for high performance
applications, greater than 100 MHz. Proper design results in
better overall performance, lower clock and DCM jitter, and
a generally more robust system. Before designing the
printed circuit board (PCB) for the FPGA design, please
review XAPP623: Power Distribution System (PDS) Design:
Using Bypass/Decoupling Capacitors.
Power-On Behavior
For additional power-on behavior information, including I/O
behavior before and during configuration, refer to the
“Sequence of Events” chapter in UG332.
Spartan-3E FPGAs have a built-in Power-On Reset (POR)
circuit that monitors the three power rails required to suc-
cessfully configure the FPGA. At power-up, the POR circuit
holds the FPGA in a reset state until the V
and V
threshold levels (see
supplies reach their respective thresholds, the POR reset is
released and the FPGA begins its configuration process.
Supply Sequencing
Because the three FPGA supply inputs must be valid to
release the POR reset and can be supplied in any order,
there are no FPGA-specific voltage sequencing require-
ments. Applying the FPGA’s V
V
Although the FPGA has no specific voltage sequence
requirements, be sure to consider any potential sequencing
requirement of the configuration device attached to the
FPGA, such as an SPI serial Flash PROM, a parallel NOR
Flash PROM, or a microcontroller. For example, Flash
PROMs have a minimum time requirement before the
PROM can be selected and this must be considered if the
3.3V supply is the last in the sequence. See
cautions if 3.3V Supply is Last in Sequence
details.
112
CCINT
CCO
supply uses the least I
Bank 2 supplies reach their respective input
Table 74
Xilinx Power Corner
CCINT
in Module 3). After all three
CCAUX
current.
supply before the
Power-On Pre-
CCINT
website pro-
, V
for more
CCAUX
www.xilinx.com
,
When all three supplies are valid, the minimum current
required to power-on the FPGA equals the worst-case qui-
escent current, specified in
not require Power-On Surge (POS) current to successfully
configure.
Surplus I
If the V
the FPGA might draw a surplus I
the I
page
might be a few hundred milliamperes under nominal condi-
tions, significantly less than the instantaneous current con-
sumed by the bypass capacitors at power-on. However, the
surplus current immediately disappears when the V
supply is applied, and, in response, the FPGA’s I
escent current demand drops to the levels specified in
Table
current to successfully power-on and configure. If applying
V
have a foldback feature that could inadvertently shut down
in the presence of the surplus current.
Configuration Data Retention, Brown-Out
The FPGA’s configuration data is stored in robust CMOS
configuration latches. The data in these latches is retained
even when the voltages drop to the minimum levels neces-
sary to preserve RAM contents, as specified in
If, after configuration, the V
below its data retention voltage, the current device configu-
ration must be cleared using one of the following methods:
•
•
The POR circuit does not monitor the VCCO_2 supply after
configuration. Consequently, dropping the VCCO_2 voltage
does not reset the device by triggering a Power-On Reset
(POR) event.
No Internal Charge Pumps or Free-Running
Oscillators
Some system applications are sensitive to sources of ana-
log noise. Spartan-3E FPGA circuitry is fully static and does
not employ internal charge pumps.
The CCLK configuration clock is active during the FPGA
configuration process. After configuration completes, the
CCLK oscillator is automatically disabled unless the Bit-
stream Generator (BitGen) option Persist=Yes.
CCINT
Force the V
minimum Power On Reset (POR) voltage threshold
(Table
Assert PROG_B Low.
CCINT
121. The momentary additional I
79. The FPGA does not use or require the surplus
CCINT
before V
CCINT
74).
quiescent current levels specified in
supply is applied before the V
CCAUX
CCAUX
if V
CCINT
or V
, ensure that the regulator does not
CCINT
Table
Applied before V
CCAUX
DS312-2 (v3.8) August 26, 2009
CCINT
supply voltage below the
79. Spartan-3E FPGAs do
or V
CCINT
Product Specification
current in addition to
CCINT
surplus current
CCAUX
supply drops
Table
CCAUX
CCINT
Table 79,
supply,
CCAUX
76.
qui-
R