XC6SLX9-L1CSG324I Xilinx Inc, XC6SLX9-L1CSG324I Datasheet - Page 39
![IC FPAG SPARTAN 6 9K 324CSGBGA](/photos/18/28/182878/xc6slx45-2csg324c_sml.jpg)
XC6SLX9-L1CSG324I
Manufacturer Part Number
XC6SLX9-L1CSG324I
Description
IC FPAG SPARTAN 6 9K 324CSGBGA
Manufacturer
Xilinx Inc
Series
Spartan® 6 LXr
Specifications of XC6SLX9-L1CSG324I
Number Of Logic Elements/cells
9152
Number Of Labs/clbs
715
Total Ram Bits
589824
Number Of I /o
200
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-LFBGA, CSPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC6SLX9-L1CSG324I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Input/Output Delay Switching Characteristics
Table 38: IODELAY2 Switching Characteristics
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
T
T
T
T
T
T
T
T
T
T
T
T
F
T
T
IODCCK_CAL
IODCCK_CE
IODCCK_INC
IODCCK_RST
TAP1
TAP2
TAP3
TAP4
TAP5
TAP6
TAP7
TAP8
MINCAL
IODDO_IDATAIN
IODDO_ODATAIN
Delay depends on IODELAY2 tap setting. See
Maximum delay = integer (number of taps/8) T
and hold report. Minimum delay is greater than 30% of the maximum delay. Tap delays can vary by device. See TRACE report for actual
values.
Spartan-6 -1L devices only support tap 0.
(2)
Symbol
/ T
/ T
/ T
/ T
IODCKC_CE
IODCKC_INC
IODCKC_RST
IODCKC_CAL
CAL pin Setup/Hold with respect to CK
CE pin Setup/Hold with respect to CK
INC pin Setup/Hold with respect to CK
RST pin Setup/Hold with respect to CK
Maximum tap 1 delay
Maximum tap 2 delay
Maximum tap 3 delay
Maximum tap 4 delay
Maximum tap 5 delay
Maximum tap 6 delay
Maximum tap 7 delay
Maximum tap 8 delay
Minimum allowed bit rate for calibration in variable
mode: VARIABLE_FROM_ZERO,
VARIABLE_FROM_HALF_MAX, and
DIFF_PHASE_DETECTOR.
Propagation delay through IODELAY2
Propagation delay through IODELAY2
TRACE
TAP8
+ T
Description
report for actual values.
TAPn
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
(where n equals the remainder). For minimum delay consult the TRACE setup
Note 1
Note 1
–0.13
–0.03
–0.02
0.28
0.17
0.10
0.02
0.12
108
171
207
212
322
188
40
95
-3
8
Note 1
Note 1
–0.13
–0.03
–0.02
Speed Grade
0.33
0.17
0.12
0.03
0.15
-3N
120
141
194
249
276
341
188
14
66
Note 1
Note 1
–0.13
–0.02
–0.01
0.25
0.06
0.22
0.48
0.18
140
166
231
292
343
424
188
16
77
-2
Note 3
Note 3
-1L
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
Mb/s
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
–
–
39