XC3S500E-4PQG208I Xilinx Inc, XC3S500E-4PQG208I Datasheet - Page 133
![IC FPGA SPARTAN-3E 500K 208-PQFP](/photos/6/71/67100/pq208_sml.jpg)
XC3S500E-4PQG208I
Manufacturer Part Number
XC3S500E-4PQG208I
Description
IC FPGA SPARTAN-3E 500K 208-PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4PQG208I
Package / Case
208-MQFP, 208-PQFP
Mounting Type
Surface Mount
Voltage - Supply
1.1 V ~ 3.465 V
Operating Temperature
-40°C ~ 100°C
Number Of I /o
158
Number Of Logic Elements/cells
*
Number Of Gates
*
No. Of Logic Blocks
1564
No. Of Gates
500000
No. Of Macrocells
10476
Family Type
Spartan-3E
No. Of Speed Grades
4
No. Of I/o's
158
Clock
RoHS Compliant
Total Ram Bits
368640
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4PQG208I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Table 94:
DS312-3 (v3.8) August 26, 2009
Product Specification
LVCMOS25 with 12mA Drive and
Single-Ended Standards
LVTTL
LVCMOS33
LVCMOS25
Signal Standard (IOSTANDARD)
Fast Slew Rate to the Following
Convert Output Time from
Output Timing Adjustments for IOB
R
Slow
Slow
Slow
Fast
Fast
Fast
12 mA
16 mA
12 mA
16 mA
12 mA
16 mA
12 mA
16 mA
12 mA
12 mA
2 mA
2 mA
2 mA
2 mA
2 mA
2 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
Speed Grade
5.20
2.32
1.83
0.64
0.68
0.41
4.80
1.88
1.39
0.32
0.28
0.28
5.08
1.82
1.00
0.66
0.40
0.41
4.68
1.46
0.38
0.33
0.28
0.28
4.04
2.17
1.46
1.04
0.65
3.53
1.65
0.44
0.20
Adjustment
-5
0
Add the
Below
5.29
4.21
5.41
2.41
1.90
0.67
0.70
0.43
5.00
1.96
1.45
0.34
0.30
0.30
1.89
1.04
0.69
0.42
0.43
4.87
1.52
0.39
0.34
0.30
0.30
2.26
1.52
1.08
0.68
3.67
1.72
0.46
0.21
-4
0
Units
www.xilinx.com
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Table 94:
Notes:
1.
2.
LVCMOS25 with 12mA Drive and
LVCMOS18
LVCMOS15
LVCMOS12
HSTL_I_18
HSTL_III_18
PCI33_3
PCI66_3
SSTL18_I
SSTL2_I
Differential Standards
LVDS_25
BLVDS_25
MINI_LVDS_25
LVPECL_25
RSDS_25
DIFF_HSTL_I_18
DIFF_HSTL_III_18
DIFF_SSTL18_I
DIFF_SSTL2_I
Signal Standard (IOSTANDARD)
Fast Slew Rate to the Following
Convert Output Time from
The numbers in this table are tested using the methodology
presented in
set forth in
These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
Output Timing Adjustments for IOB
Table
Table 95
Slow
Slow
Slow
Fast
Fast
Fast
77,
Table
DC and Switching Characteristics
and are based on the operating conditions
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
2 mA
4 mA
6 mA
2 mA
2 mA
80, and
Table
–0.55
–0.56
–0.48
–0.20
Speed Grade
5.03
3.08
2.39
1.83
3.98
2.04
1.09
0.72
4.49
3.81
2.99
3.25
2.59
1.47
6.36
4.26
0.33
0.53
0.44
0.44
0.24
0.04
0.42
0.53
0.40
0.44
Adjustment
-5
Input Only
Add the
Below
82.
–0.56
–0.20
–0.55
–0.48
5.24
3.21
2.49
1.90
4.15
2.13
1.14
0.75
4.68
3.97
3.11
3.38
2.70
1.53
6.63
4.44
0.34
0.55
0.46
0.46
0.25
0.04
0.42
0.55
0.40
0.44
-4
(Continued)
Units
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133
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