XC3S500E-4FTG256I Xilinx Inc, XC3S500E-4FTG256I Datasheet - Page 219
![IC FPGA SPARTAN-3E 500K 256FTBGA](/photos/6/71/67101/pk053-256_sml.jpg)
XC3S500E-4FTG256I
Manufacturer Part Number
XC3S500E-4FTG256I
Description
IC FPGA SPARTAN-3E 500K 256FTBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S500E-4FTG256I
Number Of Logic Elements/cells
10476
Number Of Labs/clbs
1164
Total Ram Bits
368640
Number Of I /o
190
Number Of Gates
500000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-LBGA
Package
256FTBGA
Family Name
Spartan®-3E
Device Logic Cells
10476
Device Logic Units
1164
Device System Gates
500000
Number Of Registers
9312
Maximum Internal Frequency
572 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
190
Ram Bits
368640
For Use With
122-1536 - KIT STARTER SPARTAN-3E
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S500E-4FTG256I
Manufacturer:
INTERSIL
Quantity:
4 300
Company:
Part Number:
XC3S500E-4FTG256I
Manufacturer:
XILINX35
Quantity:
350
Company:
Part Number:
XC3S500E-4FTG256I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S500E-4FTG256I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 152: FG400 Package Pinout (Continued)
DS312-4 (v3.8) August 26, 2009
Product Specification
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
IO_L31N_2/VS1/A18
IO_L31P_2/VS2/A19
IO_L32N_2/CCLK
IO_L32P_2/VS0/A17
IP
IP
IP_L02N_2
IP_L02P_2
IP_L05N_2
IP_L05P_2
IP_L08N_2
IP_L08P_2
IP_L11N_2
IP_L11P_2
IP_L14N_2/VREF_2
IP_L14P_2
IP_L17N_2/M2/GCLK1
IP_L17P_2/RDWR_B/
GCLK0
IP_L20N_2
IP_L20P_2
IP_L23N_2/VREF_2
IP_L23P_2
IP_L26N_2
IP_L26P_2
IP_L29N_2
IP_L29P_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
VCCO_2
IO_L01N_3
IO_L01P_3
IO_L02N_3/VREF_3
IO_L02P_3
IO_L03N_3
IO_L03P_3
IO_L04N_3
R
XC3S1200E
XC3S1600E
Pin Name
FG400
W18
W19
W16
W11
W17
Ball
R12
R11
U14
Y18
Y19
T16
T10
P12
P11
T12
T13
T14
V14
V15
Y16
W3
W2
W6
W5
U6
R8
U8
D2
D3
C1
Y2
V6
Y6
T8
T9
E3
E4
B1
E1
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
DUAL/
DUAL/
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
GCLK
GCLK
DUAL
DUAL
DUAL
DUAL
VREF
VREF
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
www.xilinx.com
Table 152: FG400 Package Pinout (Continued)
Bank
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L04P_3
IO_L05N_3
IO_L05P_3
IO_L06N_3
IO_L06P_3
IO_L07N_3
IO_L07P_3
IO_L08N_3
IO_L08P_3
IO_L09N_3/VREF_3
IO_L09P_3
IO_L10N_3
IO_L10P_3
IO_L11N_3
IO_L11P_3
IO_L12N_3
IO_L12P_3
IO_L13N_3
IO_L13P_3
IO_L14N_3/LHCLK1
IO_L14P_3/LHCLK0
IO_L15N_3/LHCLK3/IRDY2
IO_L15P_3/LHCLK2
IO_L16N_3/LHCLK5
IO_L16P_3/LHCLK4/TRDY2
IO_L17N_3/LHCLK7
IO_L17P_3/LHCLK6
IO_L18N_3
IO_L18P_3
IO_L19N_3
IO_L19P_3
IO_L20N_3/VREF_3
IO_L20P_3
IO_L21N_3
IO_L21P_3
IO_L22N_3
IO_L22P_3
IO_L23N_3
IO_L23P_3
IO_L24N_3
XC3S1200E
XC3S1600E
Pin Name
Pinout Descriptions
FG400
Ball
G4
G3
G5
H3
H7
M1
M3
M7
M8
M4
M5
N6
M6
N2
N4
R1
D1
F3
F4
F1
F2
H5
H2
H6
K6
K2
K3
K7
N1
P7
N7
N3
J4
J3
J1
J2
J6
L7
L1
L3
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
VREF
VREF
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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