XC3SD1800A-4CSG484C Xilinx Inc, XC3SD1800A-4CSG484C Datasheet - Page 48
![SPARTAN-3ADSP FPGA 1800K 484CSA](/photos/6/73/67348/pk223-cs484_sml.jpg)
XC3SD1800A-4CSG484C
Manufacturer Part Number
XC3SD1800A-4CSG484C
Description
SPARTAN-3ADSP FPGA 1800K 484CSA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD1800A-4CSG484C
Total Ram Bits
1548288
Number Of Logic Elements/cells
37440
Number Of Labs/clbs
4160
Number Of I /o
309
Number Of Gates
1800000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA, CSPBGA
No. Of Logic Blocks
37440
No. Of Gates
1800000
No. Of Macrocells
37440
Family Type
Spartan-3A
No. Of Speed Grades
4
No. Of I/o's
309
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1537
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD1800A-4CSG484C
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC3SD1800A-4CSG484C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Phase Shifter (PS)
Table 40: Recommended Operating Conditions for the PS in Variable Phase Mode
Table 41: Switching Characteristics for the PS in Variable Phase Mode
Notes:
1.
2.
3.
Miscellaneous DCM Timing
Table 42: Miscellaneous DCM Timing
DS610 (v3.0) October 4, 2010
Product Specification
Phase Shifting Range
MAX_STEPS
FINE_SHIFT_RANGE_MIN
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
Operating Frequency Ranges
PSCLK_FREQ
(FPSCLK)
Input Pulse Requirements
PSCLK_PULSE
DCM_RST_PW_MIN
The numbers in this table are based on the operating conditions set forth in
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
The DCM_DELAY_STEP values are provided at the bottom of
Symbol
Symbol
Symbol
(2,3)
Frequency for the PSCLK input
PSCLK pulse width as a percentage of the PSCLK period
Minimum guaranteed delay for variable phase shifting
Maximum allowed number of
DCM_DELAY_STEP steps for a given
CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double
the effective clock period.
Minimum duration of a RST pulse width
Description
Description
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Description
Table
37.
CLKIN < 60 MHz
CLKIN ≥ 60 MHz
Table 7
and
Table
40%
Min
1
±[INTEGER(10 • (T
±[INTEGER(15 • (T
40.
DCM_DELAY_STEP_MAX]
DCM_DELAY_STEP_MIN]
-5
Phase Shift Amount
60%
Speed Grade
Max
167
±[MAX_STEPS •
±[MAX_STEPS •
Min
3
40%
Min
1
CLKIN
CLKIN
Max
-4
–
– 3 ns))]
– 3 ns))]
Max
60%
167
CLKIN
cycles
Units
Units
MHz
Units
steps
–
ns
ns
48