XC3S2000-4FGG676C Xilinx Inc, XC3S2000-4FGG676C Datasheet - Page 92
![SPARTAN-3A FPGA 2M STD 676-FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC3S2000-4FGG676C
Manufacturer Part Number
XC3S2000-4FGG676C
Description
SPARTAN-3A FPGA 2M STD 676-FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet
1.XC3S50-4VQG100C.pdf
(217 pages)
Specifications of XC3S2000-4FGG676C
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
5120
Total Ram Bits
737280
Number Of I /o
489
Number Of Gates
2000000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S2000-4FGG676C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S2000-4FGG676C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Spartan-3 FPGA Family: DC and Switching Characteristics
Configuration and JTAG Timing
Table 64: Power-On Timing and the Beginning of Configuration
92
Notes:
1.
2.
3.
The numbers in this table are based on the operating conditions set forth in
V
Power-on reset and the clearing of configuration memory occurs during this period.
This specification applies only for the Master Serial and Master Parallel modes.
CCINT
Symbol
T
T
T
T
ICCK
POR
T
PROG
V
V
V
PROG_B
INIT_B
CCLK
PL
Notes:
1.
2.
3.
INIT
(Supply)
(Supply)
(Supply)
(Input)
(Open-Drain)
(Output)
CCINT
CCAUX
CCO
(2)
, V
(2)
(3)
The V
The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
CCO
Bank 4
, and V
CCINT
The time from the application of V
Bank 4 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
The width of the low-going pulse on the PROG_B pin
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
Minimum Low pulse width on INIT_B output
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
, V
Figure 34: Waveforms for Power-On and the Beginning of Configuration
CCAUX
CCAUX
lines.
, and V
CCO
1.0V
2.0V
1.0V
supplies may be applied in any order.
Description
CCINT
T
T
www.xilinx.com
POR
PROG
, V
CCAUX
, and V
T
PL
CCO
Table
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
All
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
All
All
T
31. This means power must be applied to all
ICCK
Device
DS099-3 (v2.5) December 4, 2009
All Speed Grades
0.25
Min
250
0.3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DS099-3_03_120604
Product Specification
Max
4.0
5
5
5
5
7
7
7
7
2
2
2
2
3
3
3
3
-
-
1.2V
2.5V
Units
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
μs
ns
μs
R
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