XC3SD3400A-4CS484C Xilinx Inc, XC3SD3400A-4CS484C Datasheet - Page 7
![SPARTAN-3ADSP FPGA 3400K 484CSA](/photos/6/73/67348/pk223-cs484_sml.jpg)
XC3SD3400A-4CS484C
Manufacturer Part Number
XC3SD3400A-4CS484C
Description
SPARTAN-3ADSP FPGA 3400K 484CSA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD3400A-4CS484C
Number Of Logic Elements/cells
53712
Number Of Labs/clbs
5968
Total Ram Bits
2322432
Number Of I /o
309
Number Of Gates
3400000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA, CSPBGA
For Use With
122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD3400A-4CS484C
Manufacturer:
XILINX
Quantity:
445
Part Number:
XC3SD3400A-4CS484C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
DS610 (v3.0) October 4, 2010
Spartan-3A DSP FPGA Design Documentation
The functionality of the Spartan®-3A DSP FPGA family is described in the following documents. The topics covered in each
guide are listed.
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© Copyright 2007–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS610 (v3.0) October 4, 2010
Product Specification
DS706: Extended Spartan-3A Family Overview
UG331: Spartan-3 Generation FPGA User Guide
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UG332: Spartan-3 Generation Configuration User
Guide
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Clocking Resources
Digital Clock Managers (DCMs)
Block RAM
Configurable Logic Blocks (CLBs)
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I/O Resources
Programmable Interconnect
ISE® Software Design Tools
IP Cores
Embedded Processing and Control Solutions
Pin Types and Package Overview
Package Drawings
Powering FPGAs
Power Management
Configuration Overview
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Detailed Descriptions by Mode
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ISE iMPACT Programming Examples
MultiBoot Reconfiguration
Design Authentication using Device DNA
Distributed RAM
SRL16 Shift Registers
Carry and Arithmetic Logic
Configuration Pins and Behavior
Bitstream Sizes
Master Serial Mode using Xilinx Platform Flash
PROM
Master SPI Mode using Commodity SPI Serial
Flash PROM
Master BPI Mode using Commodity Parallel
NOR Flash PROM
Slave Parallel (SelectMAP) using a Processor
Slave Serial using a Processor
JTAG Mode
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www.xilinx.com
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For specific hardware examples, please see the Spartan-3A
DSP FPGA Starter Kit board web pages.
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Create a Xilinx user account and sign up to receive
automatic e-mail notification whenever this data sheet or
the associated user guides are updated.
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UG431: XtremeDSP DSP48A for Spartan-3A DSP
FPGAs User Guide
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XtremeDSP Starter Platform—Spartan-3A DSP
1800A Edition
http://www.xilinx.com/products/devkits
/HW-SD1800A-DSP-SB-UNI-G.htm
XtremeDSP Starter Kit—Spartan-3A DSP 1800A
Edition
http://www.xilinx.com/products/devkits
/DO-SD1800A-DSP-SK-UNI-G.htm
XtremeDSP Video Starter Kit—Spartan-3A DSP
Edition
http://www.xilinx.com/products/devkits
/DO-S3ADSP-VIDEO-SK-UNI-G.htm
Embedded Development HW/SW Kit—Spartan-3A
DSP S3D1800A MicroBlaze Processor Edition
http://www.xilinx.com/products/devkits
/DO-SD1800A-EDK-DK-UNI-G.htm
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https://secure.xilinx.com/webreg/register.do?group=my
profile&languageID=1
Spartan-3A DSP FPGA Family:
XtremeDSP DSP48A Slices
XtremeDSP DSP48A Pre-Adder
Functional Description
Product Specification
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