XCV200E-6PQ240C Xilinx Inc, XCV200E-6PQ240C Datasheet - Page 23
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XCV200E-6PQ240C
Manufacturer Part Number
XCV200E-6PQ240C
Description
IC FPGA 1.8V C-TEMP 240-PQFP
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet
1.XCV200E-6CS144C.pdf
(233 pages)
Specifications of XCV200E-6PQ240C
Number Of Logic Elements/cells
5292
Number Of Labs/clbs
1176
Total Ram Bits
114688
Number Of I /o
158
Number Of Gates
306393
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
240-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Boundary Scan Mode
In the Boundary Scan mode, configuration is done through
the IEEE 1149.1 Test Access Port. Note that the
DS022-2 (v2.8) January 16, 2006
Production Product Specification
Figure 18: SelectMAP Flowchart for Write Operations
and start-up sequences complete.
later FPGAs enter start-up phase
first FPGAs enter start-up phase
are released, DONE goes High
FPGA checks data using CRC
and pulls INIT Low on error.
clearing pass and releases
configuration memory.
FPGA starts to clear
When all DONE pins
FPGA makes a final
Once per bitstream,
INIT when finished.
R
releasing DONE.
releasing DONE.
If no errors,
If no errors,
DATA[0:7]
WRITE
BUSY
CCLK
CS
Apply Configuration Byte
Configuration Completed
Disable Data Source
Repeat Sequence A
Enter Data Source
Set WRITE = High
Set WRITE = Low
Set CS = Low
Set CS = High
End of Data?
Apply Power
Release INIT
PROGRAM
from Low
to High
Busy?
INIT?
High
Low
Yes
Yes
Figure 19: SelectMAP Write Abort Waveforms
High
Low
No
No
If used to delay
configuration
On first FPGA
On first FPGA
For any other FPGAs
Sequence A
ds003_17_090602
www.xilinx.com
PROGRAM pin must be pulled High prior to reconfiguration.
A Low on the PROGRAM pin resets the TAP controller and
no JTAG operations can be performed.
Virtex™-E 1.8 V Field Programmable Gate Arrays
Abort
DS022_46_071702
Module 2 of 4
17
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