XCV200E-6FG456I Xilinx Inc, XCV200E-6FG456I Datasheet - Page 27
![no-image](/images/no-image-200.jpg)
XCV200E-6FG456I
Manufacturer Part Number
XCV200E-6FG456I
Description
IC FPGA 1.8V I-TEMP 456-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet
1.XCV200E-6CS144C.pdf
(233 pages)
Specifications of XCV200E-6FG456I
Number Of Logic Elements/cells
5292
Number Of Labs/clbs
1176
Total Ram Bits
114688
Number Of I /o
284
Number Of Gates
306393
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
456-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCV200E-6FG456I
Manufacturer:
XilinxInc
Quantity:
3 000
- Current page: 27 of 233
- Download datasheet (2Mb)
ground. As the DLL delay taps reset to zero, glitches can
occur on the DLL clock output pins. Activation of the RST
pin can also severely affect the duty cycle of the clock out-
put pins. Furthermore, the DLL output clocks no longer
deskew with respect to one another. For these reasons,
rarely use the reset pin unless re-configuring the device or
changing the input frequency.
2x Clock Output — CLK2X
The output pin CLK2X provides a frequency-doubled clock
with an automatic 50/50 duty-cycle correction. Until the
CLKDLL has achieved lock, the CLK2X output appears as a
1x version of the input clock with a 25/75 duty cycle. This
behavior allows the DLL to lock on the correct edge with
respect to source clock. This pin is not available on the
CLKDLLHF primitive.
Clock Divide Output — CLKDV
The clock divide output pin CLKDV provides a lower fre-
quency version of the source clock. The CLKDV_DIVIDE
property controls CLKDV such that the source clock is
divided by N where N is either 1.5, 2, 2.5, 3, 4, 5, 8, or 16.
This feature provides automatic duty cycle correction such
that the CLKDV output pin always has a 50/50 duty cycle,
with the exception of noninteger divides in HF mode, where
the duty cycle is 1/3 for N=1.5 and 2/5 for N=2.5.
1x Clock Outputs — CLK[0|90|180|270]
The 1x clock output pin CLK0 represents a delay-compen-
sated version of the source clock (CLKIN) signal. The
CLKDLL primitive provides three phase-shifted versions of
the CLK0 signal while CLKDLLHF provides only the 180
phase-shifted version. The relationship between phase shift
and the corresponding period shift appears in
Table 13: Relationship of Phase-Shifted Output Clock
to Period Shift
DS022-2 (v2.8) January 16, 2006
Production Product Specification
Phase (degrees)
180
270
R
90
0
Period Shift (percent)
25%
50%
75%
0%
Table
13.
www.xilinx.com
The timing diagrams in
output characteristics.
The DLL provides duty cycle correction on all 1x clock out-
puts such that all 1x clock outputs by default have a 50/50
duty cycle. The DUTY_CYCLE_CORRECTION property
(TRUE by default), controls this feature. In order to deacti-
vate
DUTY_CYCLE_CORRECTION=FALSE property to the
DLL symbol. When duty cycle correction deactivates, the
output clock has the same duty cycle as the source clock.
The DLL clock outputs can drive an OBUF, a BUFG, or they
can route directly to destination clock pins. The DLL clock
outputs can only drive the BUFGs that reside on the same
edge (top or bottom).
Locked Output — LOCKED
To achieve lock, the DLL might need to sample several thou-
sand clock cycles. After the DLL achieves lock, the
LOCKED signal activates. The DLL timing parameter sec-
tion of the data sheet provides estimates for locking times.
To guarantee that the system clock is established prior to
the device “waking up,” the DLL can delay the completion of
the device configuration process until after the DLL locks.
The STARTUP_WAIT property activates this feature.
Until the LOCKED signal activates, the DLL output clocks
are not valid and can exhibit glitches, spikes, or other spuri-
ous movement. In particular the CLK2X output appears as a
1x clock with a 25/75 duty cycle.
Virtex™-E 1.8 V Field Programmable Gate Arrays
the
CLKDV_DIVIDE=2
DUTY_CYCLE_CORRECTION=FALSE
DUTY_CYCLE_CORRECTION=TRUE
CLK180
CLK270
CLK180
CLK270
CLKDV
CLK2X
Figure 25: DLL Output Characteristics
CLK90
CLK90
CLKIN
CLK0
CLK0
DLL
0
duty
90 180 270
Figure 25
t
cycle
0
correction,
illustrate the DLL clock
90 180 270
ds022_29_121099
Module 2 of 4
attach
the
21
Related parts for XCV200E-6FG456I
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![XCV200E-6CS144C](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V C-TEMP 144-CSA
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-6CS144I](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V I-TEMP 144-CSA
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-7CS144C](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V C-TEMP 144-CSA
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-6FG256C](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V C-TEMP 256-FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-6PQ240C](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V C-TEMP 240-PQFP
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-6FG456C](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V C-TEMP 456-FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-6BG352C](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V C-TEMP 352-MBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-7CS144I](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V I-TEMP 144-CSA
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-6FG256I](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V I-TEMP 256-FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-7FG256C](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V C-TEMP 256-FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-6PQ240I](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V I-TEMP 240-PQFP
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-7PQ240C](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V C-TEMP 240-PQFP
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-8CS144C](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V C-TEMP 144-CSA
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-7FG456C](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V C-TEMP 456-FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XCV200E-7BG352C](/images/no-image3.png)
Part Number:
Description:
IC FPGA 1.8V C-TEMP 352-MBGA
Manufacturer:
Xilinx Inc
Datasheet: