XC5VLX30-1FF324C Xilinx Inc, XC5VLX30-1FF324C Datasheet - Page 336
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-1FF324C
Manufacturer Part Number
XC5VLX30-1FF324C
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-1FF324C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX30-1FF324C
Manufacturer:
XilinxInc
Quantity:
3 000
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Chapter 7: SelectIO Logic Resources
X-Ref Target - Figure 7-13
336
CLK
CLK
Q1
Q2
D1
D2
T1
T2
Figure 7-13: IODELAY and IOB in Output Mode when 3-state is Enabled
ODDR
ODDR
IDDR
The second case uses bidirectional IODELAY when the I/O is an input switching to an
output.
by the 3-state TSCONTROL signal coming from the ODDR T flip-flop. This controls the
selection of MUXes E and F for the output path and ODELAY_VALUE respectively.
Additionally, the OBUF changes to not being 3-stated and starts to drive the PAD.
Figure 7-13
DATAOUT
ODATAIN
IODELAY
shows the IOB and IODELAY moving toward the output mode as set
Delay
Chain
www.xilinx.com
TSCONTROL
MUX E
MUX F
T
ODELAY_VALUE
IDELAY_VALUE
ODATAIN
IDATAIN
OBUF
IBUF
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IOB
IODELAY_04_082107
PAD
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