XC5VLX30-1FFG324I Xilinx Inc, XC5VLX30-1FFG324I Datasheet - Page 165
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-1FFG324I
Manufacturer Part Number
XC5VLX30-1FFG324I
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-1FFG324I
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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X-Ref Target - Figure 4-31
X-Ref Target - Figure 4-32
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
(Decode Only Mode)
ECC Modes of Operation
(Register Mode)
(Register Mode)
(Register Mode)
(Register Mode)
ECCPARITY[7:0]
RDADDR[8:0]
(Latch Mode)
(Latch Mode)
(Latch Mode)
(Latch Mode)
WRADDR[8:0]
DBITERR
DBITERR
SBITERR
SBITERR
DOP[7:0]
DOP[7:0]
DO[63:0]
DO[63:0]
RDCLK
RDEN
WRCLK
DIP[7:0]
DI[63:0]
WREN
There are three types of ECC operation: standard, encode only, and decode only. The
standard ECC mode uses both the encoder and decoder.
The various modes of ECC operation in both block RAM and FIFO are shown in
Figure 4-31
supplied by the user. The FIFO WRADDR and RDADDR addresses are generated
internally from the write counter and read counter.
T1W
and
TRCCK_EN
TRCCK_ADDR
TRCCK_DI_ECC
Figure 4-31: ECC Write Operation
Figure 4-32: ECC Read Operation
TRCKO_ECC_PARITY
T1R
PA
Figure
A
a
TRCCK_EN
PA
TRCCK_ADDR
a
4-32. The block RAM WRADDR and RDADDR address inputs are
T2W
TRCKO_DO (Latch Mode)
www.xilinx.com
TRCKO_ECC_SBITERR (Latch Mode)
Single Bit Error
PA
A
T2R
PB
B
b
PB
TRCKO_DO (Register Mode)
TRCKO_ECC_SBITERR (Register Mode)
Single Bit Error
b
T3W
TRCKO_ECC_DBITERR (Latch Mode)
PA
Double Bit Error
A
PB
B
T3R
PC
C
c
PC
TRCKO_ECC_DBITERR (Register Mode)
Double Bit Error
c
T4W
PB
B
PC
C
Built-in Error Correction
T4R
PD
D
d
ug190_4_33_020707
PD
ug190_4_32_022307
d
PC
C
T5W
165
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