XC5VLX30-3FF324C Xilinx Inc, XC5VLX30-3FF324C Datasheet - Page 353
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-3FF324C
Manufacturer Part Number
XC5VLX30-3FF324C
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-3FF324C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Advanced SelectIO Logic Resources
Introduction
Input Serial-to-Parallel Logic Resources (ISERDES)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
The I/O functionality in Virtex-5 FPGAs is described in
this user guide.
•
•
•
The ISERDES in Virtex-5 FPGAs is a dedicated serial-to-parallel converter with specific
clocking and logic features designed to facilitate the implementation of high-speed source-
synchronous applications. The ISERDES avoids the additional timing complexities
encountered when designing deserializers in the FPGA fabric.
ISERDES features include:
•
•
•
Chapter 6
and their compliance with many industry standards.
Chapter 7
or DDR data.
This chapter covers additional resources:
•
•
Dedicated Deserializer/Serial-to-Parallel Converter
The ISERDES deserializer enables high-speed data transfer without requiring the
FPGA fabric to match the input data frequency. This converter supports both single
data rate (SDR) and double data rate (DDR) modes. In SDR mode, the serial-to-parallel
converter creates a 2-, 3-, 4-, 5-, 6-, 7-, or 8-bit wide parallel word. In DDR mode, the
serial-to-parallel converter creates a 4-, 6-, 8-, or 10-bit-wide parallel word.
Bitslip Submodule
The Bitslip submodule allows designers to reorder the sequence of the parallel data
stream going into the FPGA fabric. This can be used for training source-synchronous
interfaces that include a training pattern.
Dedicated Support for Strobe-based Memory Interfaces
ISERDES contains dedicated circuitry (including the OCLK input pin) to handle the
strobe-to-FPGA clock domain crossover entirely within the ISERDES block. This
allows for higher performance and a simplified implementation.
Input serial-to-parallel converters (ISERDES) and output parallel-to-serial
converters (OSERDES) support very fast I/O data rates, and allow the internal
logic to run up to 10 times slower than the I/O.
The Bitslip submodule can re-align data to word boundaries, detected with the
help of a training pattern.
covers the electrical characteristics of input receivers and output drivers,
describes the register structures dedicated for sending and receiving SDR
www.xilinx.com
Chapter 6
through
Chapter 8
Chapter 8
of
353
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