XC5VFX30T-1FFG665C Xilinx Inc, XC5VFX30T-1FFG665C Datasheet - Page 55

• Manufacturer Part Number: XC5VFX30T-1FFG665C
• Description: IC FPGA VIRTEX-5FX 30K 665-FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 FXTr

Specifications of XC5VFX30T-1FFG665C

• Number Of Logic Elements/cells: 32768
• Number Of Labs/clbs: 2560
• Total Ram Bits: 2506752
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• No. Of I/o's: 360
• Clock Management: PLL
• Core Supply Voltage Range: 0.95V To 1.05V
• Operating Frequency Max: 600MHz
• Operating: RoHS Compliant
• Package: 665FCBGA
• Family Name: Virtex®-5
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 2506752
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1583; XC5VFX30T-1FFG665C

PLL Switching Characteristics
Table 74: PLL Specification
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
2.
3.
4.
5.
F
F
F
F
F
F
F
T
T
T
T
F
F
T
RST
F
F
T
INMAX
INMIN
INJITTER
INDUTY
VCOMIN
VCOMAX
BANDWIDTH
STAPHAOFFSET
OUTJITTER
OUTDUTY
LOCKMAX
OUTMAX
OUTMIN
EXTFDVAR
PFDMAX
PFDMIN
FBDELAY
The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.
Values for this parameter are available in the Architecture Wizard.
Includes global clock buffer.
The LOCK signal must be sampled after T
expired.
Calculated as F
MINPULSE
Symbol
VCO
/128 assuming output duty cycle is 50%.
Maximum Input Clock Frequency
Minimum Input Clock Frequency
Maximum Input Clock Period Jitter
Allowable Input Duty Cycle: 19—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum PLL VCO Frequency
Maximum PLL VCO Frequency
Low PLL Bandwidth at Typical
High PLL Bandwidth at Typical
Static Phase Offset of the PLL Outputs
PLL Output Jitter
PLL Output Clock Duty Cycle Precision
PLL Maximum Lock Time
PLL Maximum Output Frequency for LX20T devices
PLL Maximum Output Frequency for LX30, LX30T, LX50,
LX50T, LX85, LX85T, LX110, LX110T, SX35T, SX50T, FX30T,
and FX70Tdevices
PLL Maximum Output Frequency for LX155, LX155T, and
FX100T devices
PLL Maximum Output Frequency for FX130T devices
PLL Maximum Output Frequency for LX220, LX220T, LX330,
LX330T, SX95T, SX240T, TX150T, TX240T, and FX200T
devices
PLL Minimum Output Frequency
External Clock Feedback Variation
Minimum Reset Pulse Width
Maximum Frequency at the Phase Frequency Detector
Minimum Frequency at the Phase Frequency Detector
Maximum External Delay in the Feedback Path
LOCKMAX
(2)
. The LOCK signal is invalid after configuration or reset until the T
Description
(4)
(1)
(1)
www.xilinx.com
(5)
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(3)
< 20% of clock input period or 1 ns Max
<20% of clock input period or 1 ns Max
3.125
1440
±150
710
400
120
100
N/A
710
650
550
N/A
550
19
19
-3
1
4
5
3 ns Max or one CLKIN cycle
Speed Grade
25/75
30/70
35/65
40/60
45/55
3.125
±200
1200
710
400
120
100
667
667
600
500
500
500
19
19
-2
1
4
5
Note 1
LOCKMAX
3.125
1000
±200
645
400
120
100
600
600
550
450
450
450
19
19
-1
1
4
5
time has
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
µs
ns
%
%
%
%
%
55