XC5VLX30-3FF676C Xilinx Inc, XC5VLX30-3FF676C Datasheet - Page 275
![IC FPGA VIRTEX-5 30K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-3FF676C
Manufacturer Part Number
XC5VLX30-3FF676C
Description
IC FPGA VIRTEX-5 30K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-3FF676C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
400
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
For Use With
HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
SSTL2_I, SSTL18_I
SSTL2_I_DCI, SSTL18_I_DCI
SSTL2_II, SSTL18_II
SSTL2_II_DCI, SSTL18_II_DCI
DIFF_SSTL2_I, DIFF_SSTL18_I
DIFF_SSTL2_I_DCI, DIFF_SSTL18_I_DCI
DIFF_SSTL2_II, DIFF_SSTL18_II
DIFF_SSTL2_II_DCI, DIFF_SSTL18_II_DCI
SSTL2_II_T_DCI, SSTL18_II_T_DCI
Class I signaling uses V
the receiver. A series resistor (25 Ω at 2.5V, 20 Ω at 1.8V) must be connected to the
transmitter output.
The DCI transmitter provides the internal series resistance (25 Ω at 2.5V, 20 Ω at 1.8V). The
DCI receiver has an internal split thevenin termination powered from V
equivalent V
Class II signaling uses V
the receiver and transmitter respectively. A series resistor (25 Ω at 2.5V, 20 Ω at 1.8V) must
be connected to the transmitter output for a unidirectional link. For a bidirectional link,
25 Ω series resistors must connected the transmitters of the transceivers.
The DCI circuits have a split thevenin termination powered from V
series resistor (25 Ω at 2.5V, 20 Ω at 1.8V). For a unidirectional link the internal series
resistance is supplied only for the transmitter. A bidirectional link has the internal series
resistor for both transmitters.
Differential SSTL 2.5V and 1.8V Class I pairs complementary single-ended SSTL_I type
drivers with a differential receiver.
Differential SSTL 2.5V and 1.8V Class I pairs complementary single-ended SSTL_II type
drivers with a differential receiver, including on-chip differential split thevenin
termination.
Differential SSTL 2.5V and 1.8V Class II pairs complementary single-ended SSTL_II type
drivers with a differential receiver. For a bidirectional link, a series resistor must be
connected to both transmitters.
Differential SSTL 2.5V and 1.8V Class II pairs complementary single-ended SSTL_II type
drivers with a differential receiver, including on-chip differential termination. DCI can be
used for unidirectional and bidirectional links.
SSTL2_II_T_DCI and SSTL18_II_T_DCI provide on-chip split thevenin termination
powered from V
standards are 3-stated. When not 3-stated, these two standards do not have parallel
termination but when invoked they have an internal series resistor (25 Ω at 2.5V and
20 Ω at 1.8V.)
TT
voltage and termination impedance.
CCO
that creates an equivalent termination voltage of V
TT
TT
www.xilinx.com
(V
(V
CCO
CCO
/2) as a parallel termination voltage to a 50 Ω resistor at
/2) as a parallel termination voltage to a 50 Ω resistor at
Specific Guidelines for I/O Supported Standards
CCO
CCO
CCO
and an internal
/2 when these
creating an
275
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