XC5VLX50-1FF1153C Xilinx Inc, XC5VLX50-1FF1153C Datasheet - Page 46
![IC FPGA VIRTEX-5 50K 1153FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-1FF1153C
Manufacturer Part Number
XC5VLX50-1FF1153C
Description
IC FPGA VIRTEX-5 50K 1153FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FF1153C
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
560
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1153-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF1153-500-G - BOARD DEV VIRTEX 5 FF1153HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50-1FF1153C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 1: Clock Resources
VHDL and Verilog Templates
46
Regional Clock Nets
In addition to global clock trees and nets, Virtex-5 devices contain regional clock nets.
These clock trees are also designed for low-skew and low-power operation. Unused
branches are disconnected. The clock trees also manage the load/fanout when all the logic
resources are used.
Regional clock nets do not propagate throughout the whole Virtex-5 device. Instead, they
are limited to only one clock region. One clock region contains four independent regional
clock nets.
To access regional clock nets, BUFRs must be instantiated. A BUFR can drive regional
clocks in up to two adjacent clock regions
can only access one adjacent region; below or above respectively. The left side BUFRs can
feed the center column I/Os.
X-Ref Target - Figure 1-23
The VHDL and Verilog code for all clocking resource primitives and ISE language
templates are available in the Libraries Guide.
BUFRs
Figure 1-23: BUFR Driving Multiple Regions
www.xilinx.com
(Figure
1-23). BUFRs in the top or bottom region
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_1_23_012306
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