XC5VLX50-3FF324C Xilinx Inc, XC5VLX50-3FF324C Datasheet - Page 332
![IC FPGA VIRTEX-5 50K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-3FF324C
Manufacturer Part Number
XC5VLX50-3FF324C
Description
IC FPGA VIRTEX-5 50K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-3FF324C
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Total Ram Bits
1769472
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50-3FF324C
Manufacturer:
XilinxInc
Quantity:
3 000
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Chapter 7: SelectIO Logic Resources
X-Ref Target - Figure 7-10
332
Figure 7-10: Basic Sections of Blocks Related to IODELAY Turnaround with Pertinent Paths Shown
CLK
CLK
Q1
Q2
D1
D2
T1
T2
IODELAY Turnaround Time Usage Model
ODDR
ODDR
IDDR
When using IODELAY in bidirectional mode, the turnaround time needs to be considered.
Figure 7-10
that applies to one use of the bidirectional IODELAY functionality.
When DELAY_SRC = IO, MUXE and MUXF dynamically selects ODATAIN or IDATAIN
and ODELAY_VALUE or IDELAY_VALUE inside the IODELAY block.
The following Verilog code segment is used for demonstrating bidirectional IODELAY:
IDDR #(
)IDDR_INST (
);
IOBUF #(
)IOBUF_INST (
);
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("SYNC")
.C(clk),
.CE(1'b1),
.D(DATAOUT),
.R(1'b0),
.S(1'b0),
.Q1(Q1),
.Q2(Q2)
.IOSTANDARD ("LVCMOS25")
.I(DATAOUT),
.T(TSCONTROL),
.O(IDATAIN),
.IO(IOPAD_DATA)
shows a simplified block diagram of the IODELAY in the Virtex-5 FPGA IOB
DATAOUT
ODATAIN
IODELAY
Delay
Chain
www.xilinx.com
TSCONTROL
MUX E
MUX F
T
ODELAY_VALUE
IDELAY_VALUE
ODATAIN
IDATAIN
OBUF
IBUF
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IOB
IODELAY_01_081407
PAD
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