XC4VFX60-11FFG672C Xilinx Inc, XC4VFX60-11FFG672C Datasheet - Page 357
XC4VFX60-11FFG672C
Manufacturer Part Number
XC4VFX60-11FFG672C
Description
IC FPGA VIRTEX-4 FX 60K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX60-11FFG672C
Number Of Logic Elements/cells
56880
Number Of Labs/clbs
6320
Total Ram Bits
4276224
Number Of I /o
352
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
For Use With
HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Output DDR Primitive (ODDR)
R
Figure 7-25
signals.
ODDR primitive.
Table 7-11: ODDR Port Signals
Table 7-12: ODDR Attributes
Q
C
CE
D1 and D2
R
S
DDR_CLK_EDGE
INIT
SRTYPE
Attribute Name
Name
Port
Table 7-12
shows the ODDR primitive block diagram.
Data output (DDR)
Clock input port
Clock enable port
Data inputs
Reset
Set
describes the various attributes available and default values for the
Function
Figure 7-25: ODDR Primitive Block Diagram
respect to clock edge
Sets the initial value for Q port
Set/Reset type with respect to clock (C)
Sets the ODDR mode of operation with
www.xilinx.com
CE
D1
D2
C
ODDR register output.
ODDR register inputs.
The C pin represents the clock input pin.
CE represents the clock enable pin. When asserted Low,
this port disables the output clock driving port Q.
Synchronous/Asynchronous reset pin. Reset is asserted
High.
Synchronous/Asynchronous set pin. Set is asserted
High.
Description
R
S
ODDR
ug070_7_25_080104
Table 7-11
Description
Q
OPPOSITE_EDGE
(default), SAME_EDGE
0 (default), 1
ASYNC, SYNC (default)
lists the ODDR port
Possible Values
OLOGIC Resources
357
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