XC5VLX110-1FF676C Xilinx Inc, XC5VLX110-1FF676C Datasheet - Page 370
![IC FPGA VIRTEX-5 110K 676FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX110-1FF676C
Manufacturer Part Number
XC5VLX110-1FF676C
Description
IC FPGA VIRTEX-5 110K 676FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX110-1FF676C
Number Of Logic Elements/cells
110592
Number Of Labs/clbs
8640
Total Ram Bits
4718592
Number Of I /o
440
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
676-BBGA, FCBGA
For Use With
HW-V5-ML523-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF676-500-G - BOARD DEV VIRTEX 5 FF676
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Part Number:
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Chapter 8: Advanced SelectIO Logic Resources
Output Parallel-to-Serial Logic Resources (OSERDES)
370
Data Parallel-to-Serial Converter
The OSERDES in Virtex-5 devices is a dedicated parallel-to-serial converter with specific
clocking and logic resources designed to facilitate the implementation of high-speed
source-synchronous interfaces. Every OSERDES module includes a dedicated serializer for
data and 3-state control. Both Data and 3-state serializers can be configured in SDR and
DDR mode. Data serialization can be up to 6:1 (10:1 if using
3-state serialization can be up to 4:1.
Figure 8-14
components and features of the block.
X-Ref Target - Figure 8-14
The data parallel-to-serial converter in one OSERDES blocks receives two to six bits of
parallel data from the fabric (10:1 if using
and presents it to the IOB via the OQ outputs. Parallel data is serialized from lowest order
data input pin to highest (i.e., data on the D1 input pin is the first bit transmitted at the OQ
pins). The data parallel-to-serial converter is available in two modes: single-data rate
(SDR) and double-data rate (DDR).
The OSERDES uses two clocks, CLK and CLKDIV, for data rate conversion. CLK is the
high-speed serial clock, CLKDIV is the divided parallel clock. It is assumed that CLK and
CLKDIV are phase aligned.
Prior to use, a reset must be applied to the OSERDES. The OSERDES contains an internal
counter that controls dataflow. Failure to synchronize the reset with the CLKDIV will
produce an unexpected output.
CLKDIV in all modes.
CLKDIV
D1 - D6
T1 - T4
OCE
TCE
CLK
SR
shows a block diagram of the OSERDES, highlighting all the major
Parallel-to-Serial Converter
Parallel-to-Serial Converter
Figure 8-14: OSERDES Block Diagram
www.xilinx.com
3-State
Data
Table 8-5
OSERDES Width
describes the relationship between CLK and
OQ
TQ
Expansion), serializes the data,
OSERDES Width
Output Driver
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IOB
ug190_8_14_100307
Expansion).
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