XCV1600E-6BG560C Xilinx Inc, XCV1600E-6BG560C Datasheet - Page 19
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XCV1600E-6BG560C
Manufacturer Part Number
XCV1600E-6BG560C
Description
IC FPGA 1.8V C-TEMP 560-MBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet
1.XCV200E-6CS144C.pdf
(233 pages)
Specifications of XCV1600E-6BG560C
Number Of Logic Elements/cells
34992
Number Of Labs/clbs
7776
Total Ram Bits
589824
Number Of I /o
404
Number Of Gates
2188742
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
560-LBGA, Metal
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Table 9
each device.
Table 9: Virtex-E Bitstream Lengths
Slave-Serial Mode
In slave-serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other source of
serial configuration data. The serial bitstream must be set
up at the DIN input pin a short time before each rising edge
of an externally generated CCLK.
Table 10: Master/Slave Serial Mode Programming Switching
DS022-2 (v2.8) January 16, 2006
Production Product Specification
CCLK
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
XCV100E
XCV200E
XCV300E
XCV400E
XCV600E
XCV50E
Device
lists the total number of bits required to configure
DIN setup/hold, slave mode
DIN setup/hold, master mode
DOUT
High time
Low time
Maximum Frequency
Frequency Tolerance, master mode with respect to nominal
R
# of Configuration Bits
Description
10,159,648
12,922,336
16,283,712
1, 875,648
1,442,016
2,693,440
3,961,632
6,587,520
8,308,992
630,048
863,840
www.xilinx.com
For more detailed information on serial PROMs, see the
PROM data sheet at
cations/ds026.pdf.
Multiple FPGAs can be daisy-chained for configuration from a
single source. After a particular FPGA has been configured,
the data for the next device is routed to the DOUT pin. The
maximum capacity for a single LOUT/DOUT write is 2
(1,048,575) 32-bit words, or 33,554,4000 bits. The data on the
DOUT pin changes on the rising edge of CCLK.
The change of DOUT on the rising edge of CCLK differs
from previous families, but does not cause a problem for
mixed configuration chains. This change was made to
improve serial configuration rates for Virtex and Virtex-E
only chains.
Figure 13
device in slave-serial mode should be connected as shown
in the right-most device.
Slave-serial mode is selected by applying <111> or <011> to
the mode pins (M2, M1, M0). A weak pull-up on the mode pins
makes slave serial the default mode if the pins are left uncon-
nected. However, it is recommended to drive the configura-
tion mode pins externally.
mode programming switching characteristics.
Table 10
shown in
INIT pins of all daisy-chained FPGAs are High.
References
Figure
Virtex™-E 1.8 V Field Programmable Gate Arrays
1/2
1/2
3
4
5
Figure
provides more detail about the characteristics
shows a full master/slave system. A Virtex-E
14. Configuration must be delayed until the
T
T
DSCK
DCC
Symbol
http://www.xilinx.com/bvdocs/publi-
T
T
T
F
CCO
CCH
CCL
CC
/T
/T
CCD
CKDS
Figure 14
+45% –30%
5.0 / 0.0
5.0 / 0.0
Values
12.0
5.0
5.0
66
shows slave-serial
Module 2 of 4
MHz, max
ns, max
ns, min
ns, min
ns, min
ns, min
Units
20
13
-1
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