XCV1600E-6FG680I Xilinx Inc, XCV1600E-6FG680I Datasheet - Page 205
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XCV1600E-6FG680I
Manufacturer Part Number
XCV1600E-6FG680I
Description
IC FPGA 1.8V I-TEMP 680-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet
1.XCV200E-6CS144C.pdf
(233 pages)
Specifications of XCV1600E-6FG680I
Number Of Logic Elements/cells
34992
Number Of Labs/clbs
7776
Total Ram Bits
589824
Number Of I /o
512
Number Of Gates
2188742
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
680-LBGA Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Table 27: FG900 Differential Pin Pair Summary
XCV600E, XCV1000E, XCV1600E
DS022-4 (v2.5) March 14, 2003
Production Product Specification
Notes:
1.
2.
3.
4.
Pair
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
AO in the XCV600E, 1000E.
AO in the XCV1000E.
AO in the XCV1600E.
AO in the XCV1000E, XCV1600E.
Bank
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
R
M10
K10
Pin
M5
M1
M8
M9
N6
N1
H4
G2
G5
H7
C2
K1
K3
K4
K7
K8
E1
E2
K9
F4
F5
L2
L5
J5
J2
P
Pin
M6
M4
M2
M7
G3
G6
N5
K2
K5
K6
H1
H5
H6
E4
D1
D2
D3
L4
L1
L3
L6
L7
L8
L9
F3
J7
J8
N
AO
NA
1
4
√
1
4
3
4
1
√
√
4
4
4
4
2
√
√
1
4
√
1
4
3
4
1
4
Functions
Other
VREF
VREF
VREF
VREF
VREF
VREF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
www.xilinx.com
1-800-255-7778
FG1156 Fine-Pitch Ball Grid Array Package
XCV1000E, XCV1600E, XCV2000E, XCV2600E, and
XCV3200E devices in the FG1156 fine-pitch Ball Grid Array
package have footprint compatibility. Pins labeled IO_VREF
can be used as either V
in the footnotes. If the pin is not used as V
as general I/O. Immediately following
Table 29
Table 28: FG1156 — XCV1000E, XCV1600E, XCV2000E,
XCV2600E, XCV3200E
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Virtex™-E 1.8 V Field Programmable Gate Arrays
for Differential Pair information.
IO_VREF_L5N_YY
IO_VREF_L2N_Y
Pin Description
IO_L4N_YY
IO_L4P_YY
IO_L5P_YY
IO_L6N_YY
IO_L0N_Y
IO_L0P_Y
IO_L1N_Y
IO_L1P_Y
IO_L2P_Y
IO_L3N_Y
IO_L3P_Y
REF
GCK3
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
or general I/O, unless indicated
REF
, it can be used
Table
Module 4 of 4
Pin #
E11
E13
E16
K11
F17
J12
J13
J14
E17
B10
D9
D16
28, see
E7
J10
J11
A5
B4
B9
H9
C5
E6
D6
A4
G8
C6
G9
F7
F8
3
3
4
3
3
3
3
3
3
3
3
119
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