XCV1000-6BG560C Xilinx Inc, XCV1000-6BG560C Datasheet - Page 43
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XCV1000-6BG560C
Manufacturer Part Number
XCV1000-6BG560C
Description
IC FPGA 2.5V C-TEMP 560-MBGA
Manufacturer
Xilinx Inc
Series
Virtex™r
Datasheet
1.XCV100-5PQ240C.pdf
(76 pages)
Specifications of XCV1000-6BG560C
Number Of Logic Elements/cells
27648
Number Of Labs/clbs
6144
Total Ram Bits
131072
Number Of I /o
404
Number Of Gates
1124022
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
560-LBGA, Metal
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XCV1000-6BG560C
Manufacturer:
XILINX
Quantity:
124
Virtex Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted
Global Clock Set-Up and Hold for LVTTL Standard, with DLL
DS003-3 (v3.2) September 10, 2002
Production Product Specification
Notes:
1.
2.
3.
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different
standards, adjust the setup time delay by the values shown in Input Delay Adjustments.
No Delay
Global Clock and IFF, with DLL
IFF = Input Flip-Flop or Latch
Set-up time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
DLL output jitter is already included in the timing calculation.
A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
Description
R
T
PSDLL
Symbol
/T
PHDLL
XCV1000
www.xilinx.com
1-800-255-7778
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
Device
XCV50
0.40 / –0.4
0.40 /–0.4
0.40 /–0.4
0.40 /–0.4
0.40 /–0.4
0.40 /–0.4
0.40 /–0.4
0.40 /–0.4
0.40 /–0.4
Min
Virtex™ 2.5 V Field Programmable Gate Arrays
1.7 /–0.4
1.7 /–0.4
1.7 /–0.4
1.7 /–0.4
1.7 /–0.4
1.7 /–0.4
1.7 /–0.4
1.7 /–0.4
1.7 /–0.4
Speed Grade
-6
1.8 /–0.4
1.9 /–0.4
1.9 /–0.4
1.9 /–0.4
1.9 /–0.4
1.9 /–0.4
1.9 /–0.4
1.9 /–0.4
1.9 /–0.4
-5
2.1 /–0.4
2.1 /–0.4
2.1 /–0.4
2.1 /–0.4
2.1 /–0.4
2.1 /–0.4
2.1 /–0.4
2.1 /–0.4
2.1 /–0.4
-4
Module 3 of 4
Units
min
min
min
min
min
min
min
min
min
ns,
ns,
ns,
ns,
ns,
ns,
ns,
ns,
ns,
19