AT40K40LV-3DQC Atmel, AT40K40LV-3DQC Datasheet - Page 2

• Manufacturer Part Number: AT40K40LV-3DQC
• Description: IC FPGA 3.3V 2304 CELL 208-PQFP
• Manufacturer: Atmel
• Series: AT40K/KLVr

Specifications of AT40K40LV-3DQC

• Number Of Logic Elements/cells: 2304
• Total Ram Bits: 18432
• Number Of I /o: 161
• Number Of Gates: 50000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Labs/clbs: -

Description
The AT40K is a family of fully PCI-compliant, SRAM-based
FPGAs with distributed 10ns programmable synchro-
nous/asynchronous, dual port/single port SRAM, 8 global
clocks, Cache Logic ability (partially or fully reconfigurable
without loss of data), automatic component generators, and
range in size from 5,000 to 50,000 usable gates. I/O counts
range from 128 to 384 in industry standard packages rang-
ing from 84-pin PLCC to 475-pin BGA, and support 3.3V
and 5V designs.
The AT40K is designed to quickly implement high perfor-
mance, large gate count designs through the use of synthe-
sis and schematic-based tools used on a PC, Sun and HP
platform. Atmel’s design tools provide seamless integration
with industry standard tools from Cadence (Concept/Ver-
ilog), Everest, Exemplar, Mentor, OrCAD, Synario, Veri-
best, and Viewlogic.
The AT40K can be used as a Coprocessor for high speed
(DSP/Processor-based) designs by implementing a variety
of compute-intensive, arithmetic functions. These include
adaptive finite impulse response (FIR) filters, fast Fourier
transforms (FFT), convolvers, interpolators and discrete-
cosine transforms (DCT) that are required for video com-
pression and decompression, encryption, convolution and
other multimedia applications.
Fast, Flexible and Efficient SRAM
The AT40K FPGA offers a patented distributed 10ns
SRAM capability where the RAM can be used without los-
ing logic resources. Multiple independent, synchronous or
asynchronous, dual port or single port RAM functions
(FIFO, scratch pad, etc.) can be created using Atmel’s
macro generator tool.
Fast, Efficient Array & Vector Multipliers
The AT40K’s patented 8-sided core cell with direct horizon-
tal, vertical and diagonal cell-to-cell connections imple-
ments ultra fast array multipliers without using any busing
resources. The AT40K’s Cache Logic capability enables a
large number of design coefficients and variables to be
implemented in a very small amount of silicon, enabling
vast improvement in system speed at much lower cost than
conventional FPGAs.
Cache Logic Design
The AT40K is the only FPGA family capable of implement-
ing Cache Logic (Dynamic full/partial logic reconfiguration,
2
AT40K
without loss of data, on-the-fly) for building adaptive logic
and systems. As new logic functions are required, they can
be loaded into the logic cache without losing the data
already there or disrupting the operation of the rest of the
chip; replacing or complementing the active logic. The
AT40K can act as a reconfigurable coprocessor.
Automatic Component Generators
The AT40K is the only FPGA family capable of implement-
ing user-defined, automatically generated, macros in multi-
ple designs; speed and functionality are unaffected by the
macro orientation or density of the target device. This
enables the fastest, most predictable and efficient FPGA
design approach and minimizes design risk by reusing
already proven functions. The Automatic Component Gen-
erators work seamlessly with industry standard schematic
and synthesis tools to create the fastest, most efficient
designs available.
The patent-pending AT40K Series architecture employs a
symmetrical grid of small yet powerful cells connected to a
flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is sur-
rounded by programmable I/O.
Devices range in size from 5,000 to 50,000 usable gates in
the initial family, and 256 to 2,304 registers. Pin locations
are consistent throughout the AT40K Series for easy
design migration in the same package footprint. AT40K
Series FPGAs utilize a reliable 0.6 micron single-poly, tri-
ple-metal CMOS process and are 100% factory-tested.
Atmel’s PC- and workstation-based Integrated Develop-
ment System is used to create AT40K Series designs. Mul-
tiple design entry methods are supported.
The Atmel architecture was developed to provide the high-
est levels of performance, functional density and design
flexibility in an FPGA. The cells in the Atmel array are
small, efficient and can implement any pair of Boolean
functions of (the same) three inputs or any single Boolean
function of four inputs. The cell’s small size leads to arrays
with large numbers of cells, greatly multiplying the function-
ality in each cell. A simple, high-speed busing network pro-
vides fast, efficient communication over medium and long
distances