AT40K20-2AQC Atmel, AT40K20-2AQC Datasheet - Page 28

• Manufacturer Part Number: AT40K20-2AQC
• Description: IC FPGA 20K GATES 100TQFP
• Manufacturer: Atmel
• Series: AT40K/KLVr

Specifications of AT40K20-2AQC

• Number Of Logic Elements/cells: 1024
• Total Ram Bits: 8192
• Number Of I /o: 78
• Number Of Gates: 30000
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-TFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Labs/clbs: -
• Other names: AT40K202AQC

AC Timing Characteristics – 5V Operation AT40K
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
Minimum times based on best case: V
Maximum delays are the average of t
28
Cell Function
Async RAM
Write
Write
Write
Write
Write
Write
Write
Write/Read
Read
Read
Read
Sync RAM
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write/Read
Read
Read
Read
AT40K/AT40KLV Series FPGA
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WECYC
WEL
WEH
AWS
AWH
DS
DH
DD
AD
OZX
OXZ
CYC
CLKL
CLKH
WCS
WCH
ACS
ACH
DCS
DCH
CD
AD
OZX
OXZ
(Minimum)
(Minimum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Maximum)
(Minimum)
(Maximum)
(Maximum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
(Minimum)
PDLH
CC
CC
= 5.25V, temperature = 0°C
and t
= 4.75V, temperature = 70°C
PDHL
Path
cycle time
we
we
wr addr setup -> we
wr addr hold -> we
din setup -> we
din hold -> we
din -> dout
rd addr -> dout
oe -> dout
oe -> dout
cycle time
clk
clk
we setup -> clk
we hold -> clk
wr addr setup -> clk
wr addr hold -> clk
wr data setup -> clk
wr data hold -> clk
clk -> dout
rd addr -> dout
oe -> dout
oe -> dout
.
8.0
3.0
3.0
2.0
0.0
2.0
0.0
4.6
3.1
1.6
2.0
8.0
3.0
3.0
2.0
0.0
2.0
0.0
2.0
0.0
3.5
3.1
1.6
2.0
-2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Pulse width low
Pulse width high
rd addr = wr addr
Pulse width low
Pulse width high
rd addr = wr addr
0896C–FPGA–04/02