XC4005E-1PQ160C Xilinx Inc, XC4005E-1PQ160C Datasheet - Page 16
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XC4005E-1PQ160C
Manufacturer Part Number
XC4005E-1PQ160C
Description
IC FPGA C-TEMP 5V 1-SPD 160-PQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4005E-4PC84C.pdf
(68 pages)
Specifications of XC4005E-1PQ160C
Number Of Logic Elements/cells
466
Number Of Labs/clbs
196
Total Ram Bits
6272
Number Of I /o
112
Number Of Gates
5000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
160-BQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4005E-1PQ160C
Manufacturer:
XILINX
Quantity:
624
XC4000E and XC4000X Series Field Programmable Gate Arrays
Input/Output Blocks (IOBs)
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals.
Figure 15
XC4000E IOB. A more complete diagram which includes
the boundary scan logic of the XC4000E IOB can be found
in
The XC4000X IOB contains some special features not
included in the XC4000E IOB. These features are high-
lighted in a simplified block diagram found in
discussed throughout this section. When XC4000X special
features are discussed, they are clearly identified in the
text. Any feature not so identified is present in both
XC4000E and XC4000X devices.
IOB Input Signals
Two paths, labeled I1 and I2 in
bring input signals into the array. Inputs also connect to an
input register that can be programmed as either an
edge-triggered flip-flop or a level-sensitive latch.
6-20
Figure 14: Detail of XC4000E Dedicated Carry Logic
Figure 40 on page
G1
G4
F2
F1
F3
shows a simplified block diagram of the
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43, in the “Boundary Scan” section.
Product Obsolete or Under Obsolescence
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Figure 15
0
1
and
Figure
Figure
16, and
16,
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I
The choice is made by placing the appropriate library sym-
bol. For example, IFD is the basic input flip-flop (rising edge
triggered), and ILD is the basic input latch (transpar-
ent-High). Variations with inverted clocks are available, and
some combinations of latches and flip-flops can be imple-
mented in a single IOB, as described in the XACT Libraries
Guide .
The XC4000E inputs can be globally configured for either
TTL (1.2V) or 5.0 volt CMOS thresholds, using an option in
the bitstream generation software. There is a slight input
hysteresis of about 300mV. The XC4000E output levels are
also configurable; the two global adjustments of input
threshold and output level are independent.
Inputs on the XC4000XL are TTL compatible and 3.3V
CMOS compatible. Outputs on the XC4000XL are pulled to
the 3.3V positive supply.
The inputs of XC4000 Series 5-Volt devices can be driven
by the outputs of any 3.3-Volt device, if the 5-Volt inputs are
in TTL mode.
Supported sources for XC4000 Series device inputs are
shown in
1
0
3
1
0
1
0
M
M
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Table
0
C
0
OUT
C
IN UP
1
1
8.
C
C
OUT0
1
IN DOWN
0
G2
G3
F4
M
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M
May 14, 1999 (Version 1.6)
TO
FUNCTION
GENERATORS
R