XC4005E-3TQ144I Xilinx Inc, XC4005E-3TQ144I Datasheet - Page 6

• Manufacturer Part Number: XC4005E-3TQ144I
• Description: IC FPGA I-TEMP 5V 3-SPD 144-TQFP
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4005E-3TQ144I

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 112
• Number Of Gates: 5000
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XC4000E and XC4000X Series Field Programmable Gate Arrays
Flip-Flops
The CLB can pass the combinatorial output(s) to the inter-
connect network, but can also store the combinatorial
results or other incoming data in one or two flip-flops, and
connect their outputs to the interconnect network as well.
The two edge-triggered D-type flip-flops have common
clock (K) and clock enable (EC) inputs. Either or both clock
inputs can also be permanently enabled. Storage element
functionality is described in
Latches (XC4000X only)
The CLB storage elements can also be configured as
latches. The two latches have common clock (K) and clock
enable (EC) inputs. Storage element functionality is
described in
Clock Input
Each flip-flop can be triggered on either the rising or falling
clock edge. The clock pin is shared by both storage ele-
ments. However, the clock is individually invertible for each
storage element. Any inverter placed on the clock input is
automatically absorbed into the CLB.
6-10
Figure 1: Simplified Block Diagram of XC4000 Series CLB (RAM and Carry Logic functions not shown)
C 1 • • • C 4
G 4
G 3
G 2
G 1
F 4
F 3
F 2
F 1
K
(CLOCK)
Table
FUNCTION
FUNCTION
2.
LOGIC
LOGIC
G1-G4
F1-F4
OF
OF
4
Product Obsolete or Under Obsolescence
G'
F'
Table
2.
H 1
FUNCTION
LOGIC
F', G',
AND
OF
H1
H'
DIN
F'
G'
H'
G'
H'
H'
F'
DIN
F'
G'
H'
D IN /H 2
Clock Enable
The clock enable signal (EC) is active High. The EC pin is
shared by both storage elements. If left unconnected for
either, the clock enable for that storage element defaults to
the active state. EC is not invertible within the CLB.
Table 2: CLB Storage Element Functionality
(active rising edge is shown)
Legend:
Power-Up or
Flip-Flop
Latch
Mode
GSR
Both
__/
SR
0*
1*
X
SR/H 0
Multiplexer Controlled
by Configuration Program
Don’t care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
EC
1
1
__/
X
X
0
1
0
X
K
CONTROL
CONTROL
S/R
S/R
EC
1*
1*
1*
X
X
X
0
D
EC
D
EC
May 14, 1999 (Version 1.6)
SD
RD
SD
RD
SR
0*
0*
0*
0*
0*
X
1
Q
Q
Bypass
Bypass
D
D
X
X
X
X
X
D
X6692
Y
X
YQ
XQ
SR
SR
D
Q
Q
D
Q
Q
R