XC4005XL-1TQ144C Xilinx Inc, XC4005XL-1TQ144C Datasheet - Page 60
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XC4005XL-1TQ144C
Manufacturer Part Number
XC4005XL-1TQ144C
Description
IC FPGA C-TEMP 3.3V 1SPD 144TQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4005E-4PC84C.pdf
(68 pages)
Specifications of XC4005XL-1TQ144C
Number Of Logic Elements/cells
466
Number Of Labs/clbs
196
Total Ram Bits
6272
Number Of I /o
112
Number Of Gates
5000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4005XL-1TQ144C
Manufacturer:
XILINX
Quantity:
1 400
Company:
Part Number:
XC4005XL-1TQ144C
Manufacturer:
XILINX
Quantity:
642
Part Number:
XC4005XL-1TQ144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
XC4000E and XC4000X Series Field Programmable Gate Arrays
Synchronous Peripheral Mode
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK
input(s) of the FPGA(s). The first byte of parallel configura-
tion data must be available at the Data inputs of the lead
FPGA a short setup time before the rising CCLK edge.
Subsequent data bytes are clocked in on every eighth con-
secutive rising CCLK edge.
The same CCLK edge that accepts data, also causes the
RDY/BUSY output to go High for one CCLK period. The pin
name is a misnomer. In Synchronous Peripheral mode it is
really an ACKNOWLEDGE signal. Synchronous operation
does not require this response, but it is a meaningful signal
for test purposes. Note that RDY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.
6-64
Figure 56: Synchronous Peripheral Mode Circuit Diagram
CONTROL
SIGNALS
DATA BUS
PROGRAM
CLOCK
4.7 k
4.7 k
Product Obsolete or Under Obsolescence
8
V
CC
RDY/BUSY
INIT
CCLK
D
PROGRAM
0-7
PERIPHERAL
M0 M1
SYNCHRO-
N/C
XC4000E/X
NOUS
DONE
DOUT
M2
NOTE:
M2 can be shorted to Ground
if not used as I/O
4.7 k
The lead FPGA serializes the data and presents the pre-
amble data (and all data that overflows the lead device) on
its DOUT pin. There is an internal delay of 1.5 CCLK peri-
ods, which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.
In order to complete the serial shift operation, 10 additional
CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each
daisy-chained device.
Synchronous Peripheral mode is selected by a <011> on
the mode pins (M2, M1, M0).
OPTIONAL
DAISY-CHAINED
FPGAs
DIN
INIT
PROGRAM
CCLK
M0 M1
XC4000E/X
SLAVE
N/C
May 14, 1999 (Version 1.6)
DOUT
DONE
M2
X9027
R