XC4020E-3HQ240I Xilinx Inc, XC4020E-3HQ240I Datasheet - Page 44

• Manufacturer Part Number: XC4020E-3HQ240I
• Description: IC FPGA I-TEMP 5V 3SPD 240-HQFP
• Manufacturer: Xilinx Inc
• Series: XC4000E/Xr

Specifications of XC4020E-3HQ240I

• Number Of Logic Elements/cells: 1862
• Number Of Labs/clbs: 784
• Total Ram Bits: 25088
• Number Of I /o: 193
• Number Of Gates: 20000
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 240-BFQFP Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

XC4000E and XC4000X Series Field Programmable Gate Arrays
Setting CCLK Frequency
For Master modes, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency
ranges from 0.5 MHz to 1.25 MHz for XC4000E and
XC4000EX devices and from 0.6 MHz to 1.8 MHz for
XC4000XL devices. In fast CCLK mode, the frequency
ranges from 4 MHz to 10 MHz for XC4000E/EX devices and
from 5 MHz to 15 MHz for XC4000XL devices. The fre-
quency is selected by an option when running the bitstream
generation software. If an XC4000 Series Master is driving
an XC3000- or XC2000-family slave, slow CCLK mode
must be used. In addition, an XC4000XL device driving a
XC4000E or XC4000EX should use slow mode. Slow mode
is the default.
Table 19: XC4000 Series Data Stream Formats
6-48
Fill Byte
Preamble Code
Length Count
Fill Bits
Start Field
Data Frame
CRC or Constant
Field Check
Extend Write Cycle
Postamble
Start-Up Bytes
Legend:
Not shaded
Light
Dark
Data Type
Product Obsolete or Under Obsolescence
11111111b
0010b
COUNT(23:0)
1111b
0b
DATA(n-1:0)
xxxx (CRC)
or 0110b
—
01111111b
xxh
Once per bitstream
Once per data frame
Once per device
Modes (D0...)
All Other
Data Stream Format
The data stream (“bitstream”) format is identical for all con-
figuration modes.
The data stream formats are shown in
data is read from left to right, and byte-parallel data is effec-
tively assembled from this serial bitstream, with the first bit
in each byte assigned to D0.
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones. This header is followed by the
actual configuration data in frames. The length and number
of frames depends on the device type (see
Table
with an error check. A postamble code is required to signal
the end of data for a single device. In all cases, additional
start-up bytes of data are required to provide four clocks for
the startup sequence at the end of configuration. Long
daisy chains require additional startup bytes to shift the last
data through the chain. All startup bytes are don’t-cares;
these bytes are not included in bitstreams created by the
Xilinx software.
A selection of CRC or non-CRC error checking is allowed
by the bitstream generation software. The non-CRC error
checking tests for a designated end-of-frame field for each
frame. For CRC error checking, the software calculates a
running CRC and inserts a unique four-bit partial check at
the end of each frame. The 11-bit CRC check of the last
frame of an FPGA includes the last seven data bits.
Detection of an error results in the suspension of data load-
ing and the pulling down of the INIT pin. In Master modes,
CCLK and address signals continue to operate externally.
The user must detect INIT and initialize a new configuration
by pulsing the PROGRAM pin Low or cycling Vcc.
21). Each frame begins with a start field and ends
May 14, 1999 (Version 1.6)
Table
Table 20
19. Bit-serial
and
R