XC4020E-4HQ208C Xilinx Inc, XC4020E-4HQ208C Datasheet - Page 56
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XC4020E-4HQ208C
Manufacturer Part Number
XC4020E-4HQ208C
Description
IC FPGA C-TEMP 5V 4SPD 208-HQFP
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4005E-4PC84C.pdf
(68 pages)
Specifications of XC4020E-4HQ208C
Number Of Logic Elements/cells
1862
Number Of Labs/clbs
784
Total Ram Bits
25088
Number Of I /o
160
Number Of Gates
20000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4020E-4HQ208C
Manufacturer:
XILINX
Quantity:
101
Company:
Part Number:
XC4020E-4HQ208C
Manufacturer:
XLINX
Quantity:
5 530
Part Number:
XC4020E-4HQ208C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
XC4000E and XC4000X Series Field Programmable Gate Arrays
Configuration Timing
The seven configuration modes are discussed in detail in
this section. Timing specifications are included.
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input of the FPGA. The serial configuration bitstream must
be available at the DIN input of the lead FPGA a short
setup time before each rising CCLK edge.
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin.
Figure 52: Slave Serial Mode Programming Switching Characteristics
6-60
Figure 51: Master/Slave Serial Mode Circuit Diagram
Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.
CCLK
PROGRAM
(Output)
NOTE:
M2, M1, M0 can be shorted
to Ground if not used as I/O
4.7 K
DOUT
CCLK
DIN
DIN setup
DIN hold
DIN to DOUT
High time
Low time
Frequency
4.7 K
M2
PROGRAM
DONE
M0 M1
Product Obsolete or Under Obsolescence
XC4000E/X
MASTER
SERIAL
Description
4.7 K
DOUT
CCLK
LDC
INIT
DIN
1 T
DCC
Bit n
V
CC
4.7 K
2 T
(Low Reset Option Used)
CCD
CLK
DATA
CE
RESET/OE
1
2
3
4
5
XC1700D
Bit n - 1
4 T
Symbol
CCH
CEO
VPP
T
T
T
T
T
F
DCC
CCO
CCD
CCH
CCL
CC
+5 V
N/C
There is an internal delay of 0.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the sub-
sequent rising CCLK edge.
Figure 51
Series device in Slave Serial mode should be connected as
shown in the third device from the left.
Slave Serial mode is selected by a <111> on the mode pins
(M2, M1, M0). Slave Serial is the default mode if the mode
pins are left unconnected, as they have weak pull-up resis-
tors during configuration.
Bit n + 1
CCLK
PROGRAM
DONE
M2
DIN
M0 M1
N/C
XC4000E/X,
XC5200
SLAVE
shows a full master/slave system. An XC4000
Min
3 T
20
45
45
0
CCO
DOUT
INIT
5 T
CCL
V
4.7 K
CC
Max
4.7 K
30
10
NOTE:
M2, M1, M0 can be shorted
to V
CCLK
M2
DIN
RESET
D/P
May 14, 1999 (Version 1.6)
CC
M0
Bit n
if not used as I/O
XC3100A
M1
SLAVE
4.7 K
PWRDN
DOUT
X5379
INIT
X9025
Units
MHz
ns
ns
ns
ns
ns
R