XC4062XL-09BG560C Xilinx Inc, XC4062XL-09BG560C Datasheet - Page 6
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XC4062XL-09BG560C
Manufacturer Part Number
XC4062XL-09BG560C
Description
IC FPGA C-TEMP 3.3V 560-MBGA
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet
1.XC4005XL-09PQ160C.pdf
(15 pages)
Specifications of XC4062XL-09BG560C
Number Of Logic Elements/cells
5472
Number Of Labs/clbs
2304
Total Ram Bits
73728
Number Of I /o
384
Number Of Gates
62000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
560-LBGA, Metal
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4062XL-09BG560C
Manufacturer:
XILINX
Quantity:
455
Company:
Part Number:
XC4062XL-09BG560C
Manufacturer:
Xilinx Inc
Quantity:
10 000
XC4000E and XC4000X Series Field Programmable Gate Arrays
CLB Single-Port RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL standards.
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XC4000XL devices and are expressed in nanoseconds unless otherwise noted.
6-78
Write Operation
Address write cycle time (clock K period) 16x2
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
Read Operation
Address read cycle time
Data Valid after address change (no
Write Enable)
Address setup time before clock K
Single Port RAM
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
Size
Speed Grade
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Symbol Min Max Min Max
WCS
WCTS
WPS
WPTS
ASS
ASTS
AHS
AHTS
DSS
DSTS
DHS
DHTS
WSS
WSTS
WHS
WHTS
WOS
WOTS
RC
RCT
ILO
IHO
ICK
IHCK
9.0
9.0
4.5
4.5
2.2
2.2
2.0
2.5
2.0
1.8
4.5
6.5
1.1
2.2
0
0
0
0
0
0
-3
6.8
8.1
1.6
2.7
DS005 (v. 1.8 October 18, 1999 - Product Specification
8.4
8.4
4.2
4.2
2.0
2.0
1.9
2.3
1.8
1.7
3.1
5.5
1.0
1.9
0
0
0
0
0
0
-2
6.3
7.5
1.5
2.4
Min
7.7
7.7
3.9
3.9
1.7
1.7
1.7
2.1
1.6
1.5
2.6
3.8
0.9
1.7
0
0
0
0
0
0
-1
Max Min Max Min Max
5.8
6.9
1.3
2.2
All devices are 100%
7.4
7.4
3.7
3.7
1.7
1.7
1.7
2.1
1.6
1.5
2.6
3.8
0.8
1.6
0
0
0
0
0
0
-09
5.8
6.7
1.2
2.0
7.4
7.4
3.7
3.7
1.6
1.7
1.7
2.1
1.6
1.5
2.6
3.8
0.8
1.5
0
0
0
0
0
0
-08
5.7
6.7
1.1
1.9
R